Compilation of the final exam

1.8086 support interrupt source types up to

A128 B256 C1024 D65536

    Answer: B

  Note:      Interrupt interrupt source, interrupt vector table, the interrupt handler.

            1. interrupt source is triggered the interrupt handler, such as we click on a keyboard, external interrupt is triggered when the program is executed when the problem will discover division division division error interrupt. 

            2. The interrupt vector table is the presence of a fixed place of memory, the memory range is 0000: 0000 Dao 0000: 03FF , 1024 two memory unit, 256 interrupt vectors , in fact, there is no 256 Ge, which has a 0000: 0200-0000: 02FF this the memory is empty, when a lot of people write their own interrupt routines are often written here.

           3 interrupt handler is written in advance in a fixed place, there is the memory address of the interrupt vector table inside.

     Interrupt sources can be divided into internal and external interrupt sources interrupt sources into two categories.

       ( 1 )  External interrupt source is defined by the CPU external events triggered the interrupt. Include: general, the slow peripherals, such as keyboards, printers, mouse and the like; a data channel, such as a disk, a data acquisition device, network or the like; real time clock, such as to have the timer, the interrupt request issued; failure source, such as a power failure, peripheral failure, memory read error limit alarm and other events.

                  (2)  internal interrupt source is defined by the CPU interrupt internal event (abnormality) caused mainly includes: a CPU instruction execution interrupt INT n interrupt caused; the CPU interrupt caused some operation error such as division by 0 or the quotient exceeds the range can express register overflow; debug interrupt settings, such as a single-step interrupt breakpoint interrupt; anomalies arising from special operations, such as the limited memory, missing pages and the like.

2.8086 microcomputer: the I / O address addressing modes:

A, the independent addressing B , unified addressing C , automatic addressing D , logical addressing

       Answer: A

         Notes: Independent addressing: the peripheral register as a separate address space. IO address and the stored (memory) addressed separately and independently addressing , the I / O port address is not occupied by the address range of the memory space. Thus, in the system there is nothing to do with another memory address IO address. In this case, the need to use dedicated to CPU instructions to access a particular peripheral.

       Unified addressing: register to participate in a unified memory addressing. Peripheral interface IO register ( i.e. IO port ) and the main memory (RAM) look the same units, the address for each port occupying a memory cell, the main memory portion is divided out as IO address space. (Understood: as the peripheral register is a memory address, thereby accessing the same memory in a manner similar to the peripheral operations) is not uniform set of IO commands

                 Independent addressing --- IO space, memory space - " the I / O port" way --I / O mapping scheme

                 Unified addressing --- only memory --- " the I / O Memory" mode --- memory mapped mode (memory-mapped mode)

                          IO Port: when a register or a memory located IO spatial, called IO port.

                          IO Memory: When a register or a memory space in memory, called the IO memory.

3.8086 interrupt, the interrupt disable operation is performed in response to (hardware)

       Software, hardware, hardware and software co  instruction

 

   Different computer to interrupt the process with their own characteristics, its majority is concerned interrupt process is as follows:

     ① break off, enter the state can not respond again interrupted by hardware implementation.

     ② save breakpoints, in order to be able to return after the end of the interrupt handler to correctly break point. By hardware implementation.

     ③ interrupt service routine entry address to send PC , the interrupt service routine. By hardware but also by software.

     ④ protection field, mask character set, open break , i.e. the protective CPU in certain registers, the interrupt processing procedure is provided that allows higher interrupt acknowledgment, to enable nested interrupts. The software implementation.

     ⑤ equipment service , in fact, valid interrupt processing is implemented in this block. Implemented by a software program.

     ⑥ Exit interrupt . Upon exiting, it should be entered an uninterruptible state, that disable interrupts, masking word recovery, the recovery site, open the interrupt, the interrupt return. Implemented by software.

 

 

4.8086 when external maskable interrupt signal is generated, the CPU () signal is valid.

            A , NMI B , INTA   C , IN    D , RD

             Answer: C

Note: the INTR = INTERRUPT the Request interrupt request signal, and it is shielded ,

          NMI = Non Maskable Interrupt non-maskable interrupt request signal

          INTA = INTerrupt Acknowledgement interrupt response signal

         RD read signal pin (output), performs a stock internal I / O read of the port in the end is reading data from the memory unit or I / O data ports, depending on the M / IO signal.

      WR write signal (output), active low, the memory or I / O write operations, depending on the particular kind of operation M / IO signal.

      M / IO memory / input / output control signal (output) if this signal is high, it represents a CPU for data transfer between the memory and;

  When low, indicates CPU for data transfer between the input and output devices.

      ALE address latch enable signal (output), active high, it can not be floating.

 

   5. The following statement is correct:

A, IO address as a unified addressing, the need for specialized IO instruction B , the internal interrupt can be masked C , -8086 must respond NMI interrupt D , -8086 microcomputer interrupt vector table in physical memory rearmost

     Answer: C

Break: The so-called interrupt means CPU during normal execution of the program, due to internal / trigger external events or by a pre-arranged program, causing the CPU to temporarily interrupt the program currently running, and turn to the implementation internal / external event or program pre-arranged service routine events until after the interrupt service routine is finished, the CPU then returns to the program office is temporarily interrupted (break) to continue the original program, the process becomes interrupted.

 

Interrupt vectors: interrupt service routine entry address .

 

Interrupt vector table : all interrupts in the system and the type code corresponding to the interrupt vector according to certain rules stored in a region , the storage region is called the interrupt vector table.

 

    6.     the Add instruction execution, will not affect the CF flag correctly

    CF is an unsigned overflow flag ( i.e., the carry flag, the most significant bit generated when the recording operation into or borrow, the most significant position of a carry bit is set. 1 ), . OF is signed overflow flag (i.e., reflected signed operand results machine exceeds a range of values that can be represented, overflows 1 ).

  Example:

      mov eax, 1

     sub eax, 2

  This result is two EAX = FFFFFFFFH, and an insufficient 2 Save , there arises a borrow , CF = 1

     mov eax, 1

     add eax, -2

  This two is different , the first execution after the EAX = 1, article II -2 after taking the complement is not equal FFFFFFFEH? And FFFFFFFEH plus EAX in 1 is not equal to FFFFFFFFH is not generated also carry no borrow , CF = 0

 

 7. In order to improve the speed of memory and to be cross-art multi body correctly  

Comment:

      High Cross address code: increasing the capacity of the memory

     Low address code Cross: increase memory access speed

 

 

       8. The    number of symbols is greater than the transfer instruction JB      error   

      9. sub instructions and cmp command functions the same   error  

 

      10. 8086CPU role address adder is to convert a logical address into a physical memory address. correct

      The method of synthesis of a physical address adder address ;

         Physical address = segment address * 16 + offset

 

    11. The instruction clock cycle is

  1. CPU accesses an instruction from the main plus a CPU time to execute this instruction
  2. CPU accesses an instruction from the main time
  3. CPU that executes one instruction time
  4. Clock cycle time

Answer: A

 Instruction cycle is the time required to execute an instruction, i.e., CPU removed from memory and an instruction execution time is the sum of this instruction.

 

 

   12 assumes that the following character code parity bits, but no data error, using even parity character code is:

               A;10100001   B.01100110  C:10101000 D:1100110

      Answer: BD

   There are two types of parity: even parity bit and odd parity bit. If a given set of data bit 1

               The number is odd, then the parity bit is set to 1 , so that the total of a number is even. Given a set of data bits in a number is even, then the odd parity bit is set to 1 , such that the total 1

               The number is odd.

    13. Which of the following is not a way of caching system commonly used address mapping mode

               A, fully associative image B, set associative image C, the phase with the image D, the direct image

                 Answer: C

    14. A directly linked images, with the need to main memory into cache a plurality of the same size

              A : Area B : section C : Block D: Group

           Answer: A

 

 

    15. The set-associative image, the memory address may be regarded as composed of a multi-segment address, they are

         A, sector address, block address, block address within

         Group B, address, block address

         C, zone address, the group address within the address block,,

         D, sector address, block address, block address within a group address

       Answer: D

 

   16. If the cache address map image is directly linked manner, when the block is a conflict does not require replacement strategy

       correct

Rationale: directly connected to the image, the Cache only one block can be replaced

 

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Origin www.cnblogs.com/javabai/p/10984340.html