Enhanced instruction 1: ACALL addr11
指令执行过程：
ACALL addr11 ;(PC)+2 -> PC
;(SP)+1 -> SP, PC7-0 -> (SP)
;(SP)+1 -> SP, PC15-8 -> (SP)
;addr11 ->PC10-0,PC15-11不变
Intensive instruction 1 exam question practice:
Known (SP) = 60H, the first address of subroutine SUBTRN is 0345H, and now execute ACALL SUBTRN at 0123H.
After the double-byte instruction, (PC) = ___, (61H) = ___, (62H) = ____.
answer:
(PC)=0345H (61H)=25H (62H)=01H
Simulation diagram:
Enhanced instruction 1 Exam question extension exercise:
Known (SP) = 50H, the first address of the subroutine SUBTRN is 2620H, and now the ACALL SUBTRN at 20F6H is executed.
After the double-byte instruction, (PC) = ___, (51H) = ___, (52H) = ____.
answer:
(PC)=2620H (51H)=F8H (52H)=20H
Supplement 5 :
1，寻址实质就是如何确定操作数的单元地址
2，存储器映象是存储器在整个存储空间的地址范围
3，MCS —51 布尔处理机的存储空间是00H～ 7FH
4，定时器中断请求发生在定时时间到
5，中断响应时间是指从查询中断请求标志位到转向中断服务程序地址区入口地址所需的机器周期数（3-8个机器周期）
6，8051 的堆栈区一般开辟在用户RAM 区
Question 40
Write a program to use the pulse signal generated by toggling up and down once as the interrupt request signal of external interrupt 0 to control the turning on and off of 8 LEDs (the way of turning on and off is defined by yourself)
Note : The interrupt source refers to the event that caused the CPU interrupt.
Analysis : See the previous article for explanation of related interrupt registers
Program source code:
ORG 0000H
LJMP START
ORG 0003H
LJMP INT0ADDR
ORG 0030H
START:
MOV SP,#60H
MOV P1,#0FFH
MOV IE,#81H
MOV IP,#01H
MOV TCON,#01H
MOV A,#0FEH
MOV R6,#8
MOV R7,#8
CLR C
SJMP $
INT0ADDR:
CJNE R6,#00H,L1
AJMP L2
L1:
DEC R6
CLR C
MOV P1,A
RLC A
AJMP L4
L2:
CJNE R7,#00H,L3
MOV R6,#8
MOV R7,#8
MOV A,#0FEH
MOV P1,A
AJMP L4
L3:
SETB C
RRC A
MOV P1,A
DEC R7
L4: RETI
END
Simulation effect video:
https://www.bilibili.com/video/BV1hp4y1X7aV/
"SCM Compilation" Final Exam, Common Examination Questions and Exercises, Summary of Question Types (14), Interruption
Little knowledge point supplement 6 :
Open collector circuit (English: Open Collector, commonly known as "open collector gate" or " OC gate ") is an integrated circuit output device. The OC gate is actually just an NPN transistor, and does not output a specific voltage or current value. The OC gate is determined by the integrated circuit to which the base of the transistor is connected (the emitter of the transistor is grounded), and the collector of the transistor is opened to output. If the output device is a field effect transistor (MOSFET), it is called an open drain (English: Open Drain, commonly known as "OD gate"), and the working principle is similar. Through the OC gate device, the output terminals of the logic gate can be directly used in parallel. The parallel connection of two OC gates can realize the logical AND relationship, called " wire AND ", but a pull-up resistor should be added to the output port to connect to the power supply .
Small knowledge point supplement 7 :
51 SCM expansion method for external interrupt sources:
1, using timer overflow expansion
2, using interrupt query method expansion
3, using expansion chip
Question 41
Write a program to control the turning on and off of the 8 LEDs using the key switch shown below. Press button 1, 8 LEDs are on at the same time, press button 2, 8 LEDs are off at the same time. The default state of the 8 LEDs is the first four lights (button 2 has the highest priority)
Program source code:
ORG 0000H
LJMP START
ORG 0003H
LJMP INT0ADDR
ORG 0013H
LJMP INT1ADDR
ORG 0030H
START:
MOV SP,#60H
MOV P1,#0FFH
MOV IE,#85H
MOV IP,#04H
MOV TCON,#05H
MOV P1,#0F0H
SJMP $
INT0ADDR:
MOV P1,#00H
RETI
INT1ADDR:
MOV P1,#0FFH
RETI
END
Remarks: In practical applications, it is best to increase the delay of about 10ms for key detection for debounce.
Simulation diagram:
Power-on default state
Button 1 is pressed
Button 2 is pressed to
add a little knowledge point 8 :
Interrupt definition : refers to the CPU temporarily stops the program being executed, and transfers to execute the service program that requests the internal and external events that the CPU serves After the execution of the service program is completed, it returns to the process of the suspended program to continue running.
** NAND gate (English: NAND gate) ** is a basic logic circuit of digital circuits. It is the superposition of AND gate and NOT gate, with multiple inputs and one output. If the input is high level (1), the output is low level (0); if at least one of the input is low level (0), the output is high level (1). NAND gate can be seen as the superposition of AND gate and NAND gate.
