Android system uses java as the basis for software development platform language, NDK Android platform can run the C / C ++ code compiled into code for ARM-elf executables.
Native program generating process
Go through four steps: 1. Pretreatment 2. 3 compilation. 4 compilation. link
After the second step to compile the C code becomes ARM assembly code, NDK supports the direct use of ARM assembler file written .s
Use ARM register or memory address value stored, a total of 37 registers and 31 general purpose registers, status registers is six. ARM has seven operating modes:
1. User mode (usr): ARM normal operation
2. Fast interrupt mode (fiq): for high-speed data transmission channel processing or
3. External Interrupt Mode (irq): for general interrupt handling
4. Management mode (svc): Protected mode operating system used
5. Termination of the data access mode (abt): This mode is entered when the data or instruction prefetch termination, virtual storage and for protection
6. System Mode (sys): Run a privileged operating system tasks
7. Definition instruction for the termination mode (und): This mode is entered when an undefined instruction execution
ARM reverse mode involves only user (usr).
User mode: access registers are divided into:
Not banked registers: R0 ~ R7
Register groups: R8 ~ R14
Program Counter: R15
Current Program Status Register: CPSR
ARM two operating states: word-aligned 32-bit ARM instructions, 16-bit Thumb instruction alignment
Relationship with ARM Thumb:
|
|
Thumb |
ARM |
| Register R0 ~ R7 |
The same state |
|
| CPSR |
The same state |
|
| Registers the correspondence relationship |
FP |
R11 |
| IP |
R12 |
|
| SP |
R13 |
|
| LR |
R14 |
|
| PC |
R15 |
|
ARM assembly language program structure
1. Section definition:
.data segments: global variables, constants, and other information compiler. Then the constant breakdown of the code in .text in .rodata
.Section ARM instructions used to define the format of segments:
.section name [,”flags”[,%type[,flag_specific_arguments]]]
name section name flags segment attributes, type segment type, flag_specific_arguments platform parameters
2. Annotations and labels
Use the comment / * * / use single-line comments begin with the @
Reference numeral: Use program jumps use, the assembler to convert into an address label
Format: <label>
3. Assembly instructions:
Program with "." Assembler instruction is the beginning of the instruction, the assembler ARM instruction set are not relevant
.file: Specify the source file name
.align: Specifies alignment Code
.ascii: statement string
.global: declare a global symbol
.type: Specifies the symbol type
.word: used to store the address value
.size: setting specifies the size of the symbol eg: ". size main,.-main" current address minus the main symbol of the size of this address is the main function of
.ident: identifying the compiler to generate an executable program segment is placed into the ".comment"
Subroutines and parameter passing
Subroutines a separate function in the code, the same concept of function
Statement Method:
.global function name
.type function name,% function
Function name:
<... function body ...>
ARM function parameter passing problem: regulations,
R0 ~ R3 register is transmitted first to fourth parameters, beyond the parameters passed on the stack.
While the R0 register is used to store the return value of the function call.
Function is called before returning without having to restore the contents of these registers
ARM addressing mode
Immediate addressing
Register Addressing
Shift Register Addressing: Five shift operation
1. LSL: Logical shift left, shift register vacated by the lower patch 0
2. LSR: logical shift right, shift register vacated by the high bit 0
3. ASR: arithmetic shift right, the sign is the same, positive negative fill up 0 1
4. AOR: Rotate Right after the shift from the low to the high fill empty
5. RRX: with extended cyclic right, a right operand, the high value of the empty flag is filled with C
Register indirect addressing
Based addressing
Multi-register addressing
Stack addressing
An LDM, STM into
LDM and STM instructions prefix register addressing multiple, FA, EA, FD, ED instruction suffix
Copy Block Addressing
Continuous copying data from one address to another position memory location
LDM and STM instruction prefix, IA, DA, IB, DB instruction suffix
Relative addressing
Address label program counter PC to the current value of the base address, the offset of the instruction, the effective address of the operand after the addition.
Eg： BL NEXT
…………
NEXT:
…………