This is a major talk ROM \ RAM \ Flash of some fragmentary knowledge, the Internet can find a lot of information.
1 ROM
1.1 Overview
ROM (Read-only memory, ROM), of course, in a broad sense, there are some devices, such as Flash, EPROM, etc., it can be programmed by some means, also within the scope of the ROM. ROM is generally used to store data in the memory and some program, where the program is mostly relatively fixed program (Firmware, firmware, a strong hardware associated with programs, such as drivers and the like), where data entry is mostly cured , lookup tables, etc. will not change how entries.
1.2 The basic principle
HDL design, for small ROM, the bit width and the depth is not large, generally can be done using a combination of logic ROM. If the data is relatively large, such that 1K * 4B, to change a ROM, using standard cell Mask ROM, stores do, as shown in FIG. Baidu Encyclopedia definition of MASK ROM, is the manufacturer in order to mass production, pre-production of a ROM or EPROM have the original data as a sample, and then mass production and sample the same ROM, as this kind of mass production of ROM sample is MASK ROM, and data burning in the MASK ROM can never make changes.
1.3 Classification
One is really written on a ROM not changed; is one kind of write-once ROM (one-time Programmable read-only memory), a high-pressure antifuse technology used; one is able to be struck, write many times ROM (erasable programmable read only memory), UV erasable; one is electrically erasable EEPROM (electrically erasable programmable read only memory, EEPROM), and then later Toshiba out of Flash. Industry first and last of Flash ROM used more.
2 Flash
1.1 Principle
Non-loss of memory, is out on the basis of the evolution of the ROM. It is the current mainstream NAND and NOR. The simulation team to do flash. You can access any address. For continuous address read access, the bandwidth gap between NAND and NOR little. NAND memory block is accessed, NOR Byte can be accessed. In general, NOR access feature is relatively thin, substantially NOR launcher put in the stability and reliability are also somewhat higher; NAND better access to data blocks, the data is usually put the NAND, and lower cost.
Figure: NOR Flash timing
ale: address lock enable; general Flash does not directly integrated into the chip, if the chip integrated on the outside, increasing the number of IO, NOR solution is multiplexed address and data, when ale is high time, go on addr is the address, when ale is low and csn is low, taking the addr data.
wen: write enable; is used to indicate read or write.
rdy: FLash for chip separation and, because it is asynchronous interface, the handshaking signals are used to using rdy. For the MCU is concerned, if the small NOR flash integrated into the chip, can be used directly synchronous interface, which is the SRAM interface.
Figure: NAND Flash Timing
CLE：Chip Lock Enable；
It can be seen that data and address lines are NAND multiplexing. NAND can read and write large blocks of data, have become more Command. NAND Flash in the MCU is relatively small. Flash ROM and RAM with different, do not want to use digital tools can be generated directly, the need to simulate team to do it yourself.
3 RAM
1.1 Basic Concepts
Static Random Access Memory, static random access. Static, without refreshing, unlike DRAM refresh required at any time, but no highly integrated DRAM SRAM, the relatively large area. In addition, the speed and power consumption better than some of the DRAM.
FIG: a memory structure of the SRAM bit
6 composed of a CMOS SRAM cell tubes, Q1, and Q3 composed of inverters, Q2 and Q4 consisting of an inverter, a loop two inverters, so long as no power down, this will not become a logical ring, with trigger principle is somewhat similar. A control input Q5, Q6 for controlling the output, two tubes corresponds to the switch input and output.
1.2 Classification
single port SRAM：不会发生读写冲突，因为之后一个端口，要么读，要么写；尽量做到先写后读，或者初始化再度，否则读出来的数据有可能不对（原因是SRAM的软失效）。对于软失效，可以加一个ECC校验，例如寸10bir，其中2bit是校验位。
Two port SRAM：FOGA的读写冲突允许，但是ASIC不可以，在同一个时刻，读地址和写地址不要一样。FIFO一般是TP SRAM。
Dual port SRAM：也是两个端口A、B，可以A读B写，也可以A写B读，不在局限于只能谁读谁写。可靠性，面积和率都不是很好。
工程上，使用两个SRAM，做乒乓操作，实现TP SRAM的功能，一个读的时候，另外一个写。两个SRAM加起来面积可能比TP SRAM小一些。对于几百几K的bit位，直接用D触发器来存储比较好。
1.3 接口
SRAM有一个需要注意下，就是Redundancy接口，用于扩展SRAM的，在比较的大的memory中会用，例如cache，这个接口可选的。用法的话，举个例子这个就是说，当SRAM中有一块坏掉了，这个时候就在尾部在接一块SRAM存储，就把坏块的地址映射到新加的存储块中，这个时候就要用的Redundancy了。
1.4 时序
对于Single port SDRAM的时序，如下图：
读是在一个时钟周期完成，如果是连续写，红点处，write enable是可以一直拉低的；读的话，是要在下一个时刻才能采到数据，注意下。