RISC-V public beta platform released · CoreMark test report

1. Introduction to CoreMark

CoreMark is a benchmark test program used to evaluate CPU performance. It includes a variety of different computing tasks, including tests on floating point numbers, integers, cache, memory, etc. CoreMark test results are usually used as a reference for CPU performance. It can help developers and system administrators evaluate the performance of different processors and systems, compare the performance differences between different processors, and can also be used to test the performance of the processor. Performance in multi-threaded parallel computing.

Official website address:

https://www.eembc.org

2. Platform environment

[Hardware parameters]

Processor: SG2042 x 1

Number of cores: 64 cores

L1 Cache: I:64KB and D:64KB

L2 Cache: 1MB/Cluster

L3 Cache: 64MB System Cache

DRAM: DDR4  16Gx4

[Software Environment]

linux version: 22.10

gcc version: 10.2.0

3. Obtain source code

EEMBC hosts the CoreMark source code on GitHub. You can access the following link to obtain the source code; you can also download it locally through the git command.

Link

https://github.com/eembc/coremark

4. Compilation

The compiler used this time is a compiler that supports RVV. It has been deployed on our experience machine. You can join the group experience through the contact information at the bottom of the article.

1: First you need to modify the core_portme.mak file (add -lpthread to the LFLAGAS_END variable)

2: Add compilation parameters: -march=rv64gcv0p7_zfh_xtheadc -mabi=lp64d -mtune=c920.

After the addition is completed, the effect is as follows:

# Flag: CC
#    Use this flag to define compiler to use
CC = gcc
# Flag: CFLAGS
#    Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
PORT_CFLAGS = -O3
#===============================Alter by me===========================
PF_CFLAGS = -march=rv64gcv0p7_zfh_xtheadc -mabi=lp64d -mtune=c920
FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END) $(PF_CFLAGS)"
CFLAGS = $(PORT_CFLAGS) $(PF_CFLAGS) -I$(PORT_DIR) -Iposix -I. -DFLAGS_STR=\"$(FLAGS_STR)\"
#===============================Alter by me===========================
# Flag: NO_LIBRT
#    Define if the platform does not provide a librt
ifndef NO_LIBRT
#Flag: LFLAGS_END
#    Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). 
#    Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.
#===============================Alter by me===========================
LFLAGS_END += -lrt -lpthread 
#===============================Alter by me===========================

Single core compilation

ubuntu@perfxlab:/public/benchmark/coremark$ make compile  XCFLAGS="-DMULTITHREAD=1 -DUSE_PTHREAD"

Multi-core compilation

ubuntu@perfxlab:/public/benchmark/coremark$ make compile  XCFLAGS="-DMULTITHREAD=64 -DUSE_PTHREAD"

5. Execute coremark on SG2042

1. The single-core test results are as follows:

picture

2. The 64-core test results are as follows:

picture

6. CoreMark score rankings

The 64-core running score result of SG2042 is: 692303.531830, and the CPU main frequency is 2GHz.

According to the formula:

CoreMark / MHz = (CoreMark Score) / (Clock Frequency in MHz)

We can calculate the CoreMark / MHz of SG2042=692303.531830/2000=346.55

As can be seen from the official website, as of now (2023-8-16), a total of 767 models of CoreMark benchmark results have been uploaded.

Official website link

https://www.eembc.org/coremark/scores.php 

picture
Figure 1: Coremark scores sorted from high to low

picture
   Figure 2: Coremark/MHz scores sorted from high to low

As can be seen from the rankings (Figures 1 and 2 above), SG2042 shows impressive performance whether based on CoreMark score or CoreMark/MHz score. As the world's first RISC-V processor chip, its score already deserves full appreciation. Although there is still a certain gap between the first place and the first place, domestic chips will continue to work hard and make continuous progress. Let us cheer for the future development of domestic chips!

End of text


  • About HS-2

The HS-2 RISC-V universal motherboard is a standard mATX motherboard designed for developers jointly developed by Pengfeng Technology and its partners. It is pre-installed with a software package customized and developed by Pengfeng Technology for RISC-V high-performance servers. Including various standard benchmarks, GCC compilers supporting V extensions, computing libraries, middleware, and a variety of typical server applications.

The HS-2 RISC-V general-purpose motherboard is equipped with a domestic RISC-V 64-core processor (SG2042). SG2042 is the highest-performance RISC-V processor currently in mass production. It is mainly designed for the needs of high-performance computing and is suitable for large computing power application scenarios such as scientific computing, engineering computing, AI computing, and fusion computing.

picture

  • About the RISC-V public test platform

    picture

RISC-V high-performance processor public test cloud platform · quick use guide, download link: https://www.kdocs.cn/l/cmnYcyFIlVRx

  • RISC-V public test cloud platform series of articles

  1.  RISC-V Public Test Platform Released Stream Bandwidth Complete Test

  2.  RISC-V public beta platform released · Minecraft MohistMC

  3.  RISC-V public beta platform released·The first WEB Server "Hello RISC-V world!"

  4.  RISC-V public beta platform released·How to play k3s on SG2042

  5. "RISC-V Growth Diary" blog released, the first blog running on RISC-V server?

  6. RISC-V public beta platform released: How to play OpenMPI on SG2042

  7. RISC-V public beta platform released: Compiling The Fedora Linux Kernel Natively on RISC-V

  8.  RISC-V public beta platform released·Unix Bench complete test

  9. RISC-V public beta platform released·Using YCSB to test MySQL performance on SG2042

  10. RISC-V public beta platform released · 7-zip test

  11. RISC-V public beta platform released · CoreMark test report (this article)

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Origin blog.csdn.net/weixin_45571628/article/details/132367277
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