Novice Tutorial 01: Basic use of logic simulation tool VCS

Table of contents

foreword

Use the method of graphical interface to use VCS

1. Create a new folder to store the Verilog source code and testbench test files that need to be simulated​

2. Use the cd command to enter the path of the folder, and generate a file.list file for the files that need to be compiled

3. Use the vcs command to compile the verilog code required for simulation

4. Start the VCS graphical interface

5. Perform simulation and generate waveforms

Summarize


foreword

Zero-based digital IC for beginners, organize study notes here. Learn what to write and make progress together with everyone.

This article mainly introduces how to use the graphical interface of the logic simulation tool VCS, and the next article introduces how to write makefile scripts for simulation.


Use the method of graphical interface to use VCS

1. Create a new folder to store the Verilog source code and testbench test files that need to be simulated

2. Use the cd command to enter the folder path, and generate the file.list file for the files that need to be compiled 

The file.list file is used to store the path of all the files we need to compile, which is convenient for subsequent compilation with vcs.

If the path of the rtl file is not in the current folder, you can add the relative path of the file before -name.

find -name '*.v' > file.list
gvim file.list

3. Use the vcs command to compile the verilog code required for simulation

vcs -full64 -sverilog -debug_access+all -f file.list -timescale=1ns/1ns -l com.log

 vcs -full64 Compile source code using EDA logic simulation tool

-sverilog can recognize system verilog language

-debug_access+all compile command option, which can save various files generated during the debug process

-f file.list Read the Verilog files under each path in the file.list file

-timescale=1ns/1ns defines simulation time

-l com.log save the log file com.log

+v2k supports Verilog2001 standard

 After the compilation is complete, the simv executable file will be generated, which can be used for subsequent simulations.

4. Start the VCS graphical interface

dve &

& means to open the dve graphical interface in the background without occupying the current terminal

5. Perform simulation and generate waveforms

Enter run in the command line window to simulate

After the simulation is complete, add the waveform you want to observe

Generate the final waveform


Summarize

The above is a simple method of using VCS. If there are any mistakes in the study notes, please leave a message to correct them~

In addition, there are VCS usage skills, please leave a message to add~

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Origin blog.csdn.net/weixin_43414549/article/details/128062060