VCS software use steps

Introduction to VCS Software

VCS (verilog compiled simulator) is a compiled Verilog simulator, which fully supports the OVI standard Verilog HDL language, PLI and SDF. VCS has the highest simulation performance in the industry, its excellent memory management capability is sufficient to support tens of millions of gate-level ASIC designs, and its simulation accuracy fully meets the requirements of deep submicron ASIC Sign-Off. VCS combines the beat algorithm and the event-driven algorithm, with high performance, large-scale and high-precision characteristics, suitable for all stages from behavioral level, RTL to Sign-Off. VCS has integrated all the coverage test functions in CoverMeter and provides intelligent verification methods such as VeraLite and CycleC. VCS and Scirocco also support mixed language simulation. Both VCS and Scirocco integrate the Virsim graphical user interface, which provides interactive and post-processing analysis of simulation results. The VCS 2009.12 Linux verification library is based on the proven DesignWare verification IP benchmark, and adds support for Synopsys' Reference Verification Methodology (RVM) and intrinsic test platform, which can realize coverage-driven test platform methodology, And its runtime performance is improved by 5 times. VCS 2009.12 Linux verification library is the industry's widest standard-based verification IP product portfolio, which can be easily integrated into Verilog, SystmVerilog, VHDL and Openvera test platforms to generate bus communication and protocol violation checks. The monitor provides a comprehensive report that shows the functional coverage of the bus communication protocol. The verification IP of the VCS verification library is also included in the DesignWare library or purchased as a stand-alone kit. Main advantages:
　　● The industry's widest IP product portfolio;
　　● When using VCS & Pioneer NTB, the simulation performance is significantly improved;
　　● It can be fully configured to achieve better control of testing and faster development and testing. Easy to use Interface, and provide test platform examples, speed up the learning speed, and accelerate the development of the test platform.

File preparation

Take a two-frequency module as an example to demonstrate the simplest way to use VCS.

ClockDiv.v

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 10/13/2020
// Design Name: Sniper
// Module Name: ClockDiv
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module ClockDiv(
    input clk,
    input rst_n,
	output reg clk_div
);

always@(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		clk_div <= 1'b0;
	else
		clk_div <= ~clk_div;
end

endmodule

tb_ClockDiv.v

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 10/13/2020
// Author Name: Sniper
// Module Name: tb_ClockDiv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//

module tb_ClockDiv;

//input
reg clk;
reg rst_n;

//output
wire clk_div;

initial
begin
    clk = 0;
    rst_n = 0;

	#100;
	rst_n = 1;

end

//clock
always #5 clk = ~clk;

//DUT
ClockDiv DUT
(
    .clk(clk),
    .rst_n(rst_n),
    .clk_div(clk_div)
);

initial
begin
  $dumpfile("curve.vcd");
  $dumpvars(0,DUT);
end

initial #1000 $finish;

endmodule

VCS commands

Enter the following command in Terminal to compile the file: (You can also write the command in a shell script)

vcs -R ClockDiv.v tb_ClockDiv.v

DVE look at the waveform

Enter dve in Terminal to open the software

dve

Open the generated .vcd wave file:

Open a new waveform display window:

The display can be adjusted here:

`

Appendix: Common VCS Commands

1. In the process of learning VCS (Verilog Compile Simulator), you can use vcs -full64 -help to view the help if you encounter an unknown compilation command.
2. You may need to view the corresponding User Guide during the VCS learning process. Generally, there will be PDF files in the doc folder under the vcs installation directory.
3. VCS is to compile the source file input by the user to generate the corresponding executable file (the default is a binary simv file), and run this executable file in the subsequent simulation.

VCS syntax

$ vcs [options] source_files

Common options

-help		//vcs帮助，有各编译选项意义；

-full64		//以64位模式编译设计并创建64位可执行文件用于64位模式下的模拟;

-vpi		//允许使用vpi PLI访问例程；

-sverilog	//允许在Accellera systemVerilog规范中使用Verilog语言扩展；

-v2k		//使用Verilog 1364-2001标准；

-cpp		//使用c++编译器；

-debug_pp	//允许转储到VPD并使用UCLI命令和DVE；

-debug		//启用UCLI命令和DVE；

-debug_all	//启用UCLI命令和DVE，也使线路步进；

-notice		//启用详细的诊断消息；

+lint=[no]ID|none|all,... //使能或者禁用verilog的lint消息；

+rad			//对设计进行辐射技术优化；

+vcs+lic+wait	//如果没有可用的通知，则告诉VCS等待网络许可证；

-f <filename>	//指定一个文件，其中包含源文件和编译时选项的路径名列表；

-o <name>		//指定输出可执行文件的文件名，默认为 simv；

-R				//该选项告诉VCS在编译完后直接运行可执行程序，若没有该选项，那么vcs在编译后直接退出；

-l <filename>	//（小写字母L）如果包含-R，-RI或-RIG选项，则指定VCS记录编译消息和运行时消息的日志文件；

-Mupdate[=0]：默认情况下，VCS会在编译之间覆盖Makefile。 如果希望在编译之间保存Makefile，请输入此内容选项与0参数。输入不带0参数的参数，指定默认情况下，增量编译和更新Makefile文件；

-CFLAGS <options>	//将选项传递给C编译器，允许多个-CFLAGS，允许传递C编译器优化级别。

-timescale=<time_unit>/<time_precision>	//指明时间精度；

-ucli	//在运行时指定UCLI模式；

+incdir+<directory>		//指定包含使用`include 编译器指令指定的文件的目录，可以指定多个目录，用+字符分隔每个路径名称；

+libext+<extension>		//指定VCS仅在具有指定扩展名的Verilog库目录中搜索源文件，可以指定多个扩展名，用+字符分隔每个扩展名。例如+libext++.v指定搜索没有扩展名和库扩展名为.v的库文件。 输入-y选项时输入此选项。

+systemverilogext+<ext>	//指定包含SystemVerilog源代码的源文件的文件扩展名；

-gui[=<dve|verdi>]		//启动用户指定的图形用户界面，如果未提供参数，则在检测到有效的VCS_HOME环境变量时，VCS将启动Verdi。 否则DVE将默认启动；

-vcd <filename>			//将输出VCD文件名设置为指定文件。默认文件名为verilog.dump。Verilog源代码中的$dumpfile系统任务将覆盖此选项；

-verdi		//使用verdi图形界面；

+vcdfile+<filename>		//指定想要用于后期处理的VCD文件；

-vpd_file <filename>	//在运行时，定义VCS写入的VPD文件的替代名称，而不是缺省名称vcdplus.vpd；

+define+VCS				//定义全局的VCS，编译器在编译时如果源文件有类似`ifdef VCS等字样，那么会执行定义之后的代码。

+vcs+vcdpluson			//编译选项，加入后会使能产生vpd文件，默认文件名vcdplus.vpd