How to use the function function

topic description

In digital chip design, modules that implement specific functions are often written as functions, and then called in the main module when needed, so as to improve the reusability of the code and the level of the design, and make subsequent modifications.

Please use the function to implement a 4bit data big and small endian conversion function. Realize the conversion and output of two different inputs respectively.

The interface signal diagram of the program is as follows:

Use Verilog HDL to realize the above functions and write testbench verification.

Enter a description:

a, b: unsigned number with 4bit width

Output description:

c, d: unsigned number with 4bit width

problem solving ideas

The question is obvious, it is to examine how to use the function;

In Verilog HDL, the declaration of a function begins with the keyword function and ends with the keyword endfunction. The statements in the function need to be included with begin...end, even if there is only one sentence. The declaration template of the function is as follows:

function [range-1:0] function_name（input_declaration）;
    other_declaration ;    
    procedural_statement ;
endfunction

When a function is declared, it will implicitly declare a register variable with a width of range and a name of function_name, and the return value of the function is passed through this variable. When the register variable does not specify a bit width, the default bit width is 1. The declaration of input variables and other declarations are then made. Note that the end of the function definition needs to add ";" to end.

       function is a function used to describe functions, not to describe hardware, and sequential logic is not allowed.

       A for loop can be used in a function:

`timescale 1ns/1ns
module function_mod(
    input [3:0]a,
    input [3:0]b,
    
    output [3:0]c,
    output [3:0]d
);


    function [3:0]bit_reverse(input [3:0]data);
        integer i;
        for(i=0;i<4;i=i+1)
        begin:reverse
            bit_reverse[i] = data[3-i] ;
        end  
    endfunction

    assign  c = bit_reverse(a) ;   //调用function
    assign  d = bit_reverse(b) ;    
endmodule

So what is the difference between a for loop and generate ... for in a function?

The function is implemented in the FPGA, what resources are consumed?