/* ---STM32 register architecture---
Some common registers of the STM32 register architecture:
SCB: It belongs to the global control register area in the STM32 register architecture and plays an important role in controlling the entire MCU.
FLASH: Flash memory is responsible for storing program code and executing programs. In STM32, FLASH is divided into different areas belonging to the chip and has different protection states.
SRAM: Static Random Access Memory (SRAM) is an alternative to Dynamic Random Access Memory (DRAM). SRAM does not need to be refreshed and has better speed and reliability.
EXTI: The External Interrupt and Event Controller allows interrupt events, signals and communication to external I/O.
NVIC: The Embedded Vectored Interrupt Controller (NVIC) handles interrupts, and the NVIC has priority control that allows the highest priority interrupt to be processed without being inserted.
RCC: The Clock Controller (RCC) is responsible for controlling the clocks within the chip. It provides external high-speed clock, PLL clock and option to use internal RC clock.
GPIO: The general-purpose I/O port (GPIO) provides the input and output of the chip. Specifically, GPIO is connected to pins inside the chip, and it is usually used to perform input and output control operations on chip circuits in digital form.
TIM: A timer (TIM) is used for timing, counters and other processing. The TIM can perform timing and counting functions such as PWM (Pulse Width Modulation) generation and counter triggering from other timers to implement complex timing circuits.
UART: The serial communication interface (UART) allows the chip to send/receive communication externally. The UART has an adaptive communication speed, enabling data to be communicated bidirectionally between the two UARTs.
ADC: An analog-to-digital converter (ADC) converts an analog signal into a digital signal that the chip can read and process.
I2C: A serial interface (I2C) can be used to communicate with other devices, for input/output control of the chip, and to communicate with other chips/logos.
AFIO: Provides a flexible IO mapping method for STM32 chips
SysTick: It is commonly used for delay and time management in embedded systems.
These and other registers constitute the complete register architecture of STM32. For STM32 developers, understanding the function and usage of each register can better grasp the overall structure of chip resources, debug and repair hardware problems.
*/
/* ---SCB---
Key registers and flags contained in the SCB (System Control Block):
1 CPUID register: used to view the model and version number of the processor core.
2 INTCTRL register: Used to control interrupt processing and priority, including interrupt control of NVIC priority and SysTick timer.
3 ACTLR register: Used to enable optional features of some ARM architectures.
4 SCR register: Used to control the state and behavior of the processor, including enabling/disabling ISR, enabling/disabling low-power mode, etc.
5 CCR register: Used to control the coprocessor and instruction set status of the processor, including enabling/disabling the FPU, coprocessor and Thumb2 mode.
6 SHCSR register: Used to control the system hardware standing state, including enabling/disabling exceptions.
7 DFSR register: Used to indicate the status and fault information of the data memory.
8 MMFSR and BFSR registers: Used to indicate the access rights and status of data and instructions, including memory access exceptions, bus access exceptions, and undefined instruction exceptions.
9 ISR register: Used to indicate active exceptions or interrupts, and can also be used to clear pending exceptions and interrupts.
10 VTOR register: used to store the base address of the vector table.
11 AIRCR register: It is used to store the default state value after the processor is reset, and the processor can be reset through this register.
12 STIR register: used for software trigger interrupt, this register can be used to start a new interrupt request during interrupt response.
13 SHP register: used to control NVIC interrupt priority, including setting interrupt group and setting interrupt priority.
14 CPACR register: used to control the access rights of the coprocessor, including enabling/disabling the VFP module and NEON module, etc.
15 CFSR register: Used to indicate the status and fault information of the processor, including processor exceptions, memory access exceptions, bus access exceptions, etc.
16 HFSR register: Used to record relevant information when the processor has a hardware exception.
17 DFSR register: Used to indicate relevant information when data access is abnormal.
18 MMAR and BFAR registers: It is used to indicate the relevant information of abnormal memory address.
*/
/* ---INCLUDE---
1 AFIO_MAPR: IO mapping register, used to configure GPIO multiplexing function.
2 AFIO_EXTICR1-4: External interrupt line control registers, used to configure the GPIO pins connected to the external interrupt line.
3 AFIO_MAPR2: Used to configure the system Flash access scheme.
4 AFIO_EVCR: Event control register, used to control events and event output.
5 AFIO_MAPR_SWJ_CFG: JTAG pin configuration register, used to configure JTAG SWJ mode, this mode is used for JTAG debugging, debugging in single-wire debugging mode and board-level testing.
6 AFIO_MAPR_CAN_REMAP: CAN interface mapping register, used to configure the multiplexing mapping of CAN interface.
*/
/* ---NVIC---
1 NVIC_ISER0-NVIC_ISER3: NVIC interrupt enable registers, used to control the enable status of each interrupt.
2 NVIC_ICER0-NVIC_ICER3: NVIC interrupt disable registers, used to control the disable status of each interrupt.
3 NVIC_IPR0-NVIC_IPR95: NVIC interrupt priority registry, used to configure the priority value of each interrupt, each of which contains 4 interrupt priorities.
4 NVIC_STIR: NVIC software triggers the interrupt register, which is used to generate a new interrupt request immediately after the processor's current interrupt response ends.
5 NVIC_ICPR0-NVIC_ICPR3: NVIC interrupt clear registers, used to clear the pending status of each interrupt for the next interrupt response.
6 NVIC_ISPR0-NVIC_ISPR3: NVIC interrupt pending registers, used to suspend interrupt requests to maintain interrupt priority status.
7 NVIC_IABR0-NVIC_IABR3: NVIC interrupt activity identification registers, used to determine the activity status of each interrupt.
8 NVIC_IPR: NVIC Priority Register.
9 NVIC_ITCR: Instruction Trace and Peripheral Data Access Enable Register.
10 NVIC_ITNS: Interrupt input enable register.
*/
/* ---RCC---
1 RCC_CR: Clock control register, used to control the configuration and enable status of the internal clock source, and can be configured to enable HSE, HSI, PLL clock sources, etc.
2 RCC_CFGR: Clock configuration register, used to configure and control the frequency division and multiplication of the STM32 chip system clock, in order to adjust the frequency of the system clock and each peripheral clock.
3 RCC_APB1ENR: APB1 bus clock enable register, which controls the peripheral clock enable status on the APB1 bus, and can turn on or off the corresponding peripheral clock.
4 RCC_APB2ENR: APB2 bus clock enable register, which controls the peripheral clock enable status on the APB2 bus, and can turn on or off the corresponding peripheral clock.
5 RCC_AHBENR: AHB bus clock enable register, which controls the enable status of the peripheral clock on the AHB bus, and can turn on or off the corresponding peripheral clock.
6 RCC_CSR: Clock control and status register, used to store and control the status and reset information of the system clock.
*/
/* ---SysTick---
1 SYSTICK_CTRL Register
This register (address: 0xE000E010) is used to control the behavior of the SysTick timer. Among them, the meaning of each is as follows:
Bit 0: ENABLE, 1 means enable SysTick timer, 0 means disable.
Bit 1: TICKINT, 1 means enable SysTick timer interrupt, 0 means disable.
Bit 2: CLKSOURCE, 1 means use the processor clock as the clock source of SysTick, 0 means use the external clock source as the clock source of SysTick.
Bit 16~23: RESERVED, reserved bit, the written value will be ignored.
Bit 24~31: COUNTFLAG, 1 indicates that the SysTick timer has counted down to 0 (that is, the SysTick overflows), and 0 indicates that the SysTick counter has not overflowed.
2 SYSTICK_LOAD Register
This register (address: 0xE000E014) is used to set the reload value of the SysTick timer.
The SysTick timer counter counts down and an interrupt is issued every time the count value decreases by 1.
The load register SYSTICK_LOAD can be used to load reload values. After each interrupt, the counter will be reset to the new loaded value.
3 SYSTICK_VAL Register
This register (address: 0xE000E018) is used to read the current SysTick counter value.
Because the SysTick counter counts down, its value is the count from LOAD to 0.
4 SYSTICK_CALIB Register
This register (address: 0xE000E01C) contains the SysTick timer feature register. Among them, the meaning of each is as follows
Bit 0: TENMS, this read-only register contains the number of cycles the counter subtracts from 1 to 0 from LOAD, this value can be used to calibrate the accuracy of the external clock source.
Bit 1~23: RESERVED, reserved bit, the written value will be ignored.
Bit 23: SKEW, 1 means the current external clock source has a slope (Skew), 0 means no slope. Skew indicates the clock jitter or clock jump during the IFF mechanism (insertion and deletion flag).
Bit 24: NOREF, 1 indicates that the external clock source is not accessible, the clock can be used internally, but cannot be used for clock source calibration, 0 indicates that the external clock source is accessible.
Bit 25: RESERVED, reserved bit, the written value will be ignored.
Bit 26: SKEWCTL, 1 means enable IFF slope control, 0 means disable.
Bit 27~31: RESERVED, reserved bit, the written value will be ignored.
*/
#include <stdio.h>
int main(void)
{
printf("hello word!!!");
return 0;
}