What is cache and what is its use
Cache is a kind of memory called cache.
In terms of capacity: CPU < register < cache < DDR
In terms of speed: CPU > registers > cache > DDR
The existence of the cache is because the speed difference between the register and the DDR is too large, and the speed of the DDR is far from meeting the needs of the register (it cannot meet the needs of the CPU, so no cache will slow down the overall speed of the entire system)
The CPU supply chain of the entire system is composed of: register + cache + DDR + solid-state disk/hard disk/Flash, which is the result of a compromise after comprehensive consideration of performance and cost.
There are 32KB icache and 32KB dcache inside 210. icache is used to cache instructions; dcache is used to cache data.
The meaning of cache: The instruction is usually placed in the hard disk/Flash, read into the DDR at runtime, then read from the DDR to the register, and then sent to the CPU by the register. However, the speed of DDR is too different from the register (represented by the CPU). If the CPU finishes running a sentence and then goes to DDR to read the next sentence, the speed of the CPU will be completely dragged down by DDR. The solution is icache.
When the icache is working, it will implement and read the next few instructions next to the instruction that our CPU is running into the icache (there is a basic principle of CPU design: when the code is executed, the next sentence has a higher probability of executing the code next to the current one), When the next command is requested by the CPU, icache will first check whether there is such a command in the cache command it has prepared in advance. If there is a command, it will be directly sent to the CPU. If not, it will need to be re-read from the DDR and sent to the CPU, and at the same time perform a series of actions: Clear cache, re-cache.
Operation of BL0 on cache in iROM
First of all, all actions of icache are automatic without human intervention. All we have to do is turn on/off icache.
Secondly, icache has been turned on in BL0 of iROM of 210. So the phenomenon seen before is the phenomenon when icache is turned on.
Assembly code reads and writes cp15 to switch icache
mrc p15,0,r0,c1,c0,0; // 读出cp15的c1到r0中
bic r0, r0, #(1<<12) // bit12 置0 关icache
orr r0, r0, #(1<<12) // bit12 置1 开icache
mcr p15,0,r0,c1,c0,0;Experimental verification
Let's look at the experimental phenomena in three cases:
(1) Directly use the operation of icache in BL0
(2) Turn off icache
(3) open icache
Analysis of results:
Conclusion 1: icache is indeed enabled in irom.
Conclusion 2: LED flashes slower when the icache is turned off than when the icache is turned on, indicating that the instruction execution speed is slower.
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