I2S/PCM is a typical low-speed serial port. There are two sets of signals in two directions. We have divided the soc into soc-adif and peripheral audio-codec from the perspective of soc.
Then adif input:
sclk_i, ws_i, sdi
Of course, the three input signals are not valid at the same time, only when the adif RX slave is active, all three inputs will be valid
adif output:
sclk_o, ws_o, sdo
Only when adif TX master is used, the three outputs will be valid.
Two issues are explained below
1. When TX master and RX slave, explain how adif and codec complete bitsync;
2. When TX slave and RX master, explain how to ensure that the ws/fs sclk output by RX reaches the TX end to generate sdo, and then use ws/fs sclk at the RX end to sample correctly
In fact, the first question corresponds to the skew between time signals; the second question corresponds to the latency of time signal transmission.
First we give the magnitude of some parameters:
The register setup and hold times of adif and codec are both in a few ns
The working clocks of adif and codec are ten to hundreds of times that of sclk
Sclk (bitclk sampling clock) has a maximum of more than ten MHz, so the period of sclk is on the order of 100ns [ For all audio sampling rates and sampling depths, please refer to another article TODO ]
1. I2S/PCM Synchronization
I2S/PCM has its own frame synchronization signal. For I2S, the falling edge of ws is the frame start; for PCM, the rising edge of fs is the frame start.
So how to ensure bit synchronization? Different from the complex bit synchronization circuit of the high-speed serial interface, the bit synchronization of I2S/PCM is very simple, mainly completed by the following mechanisms:
- Set skew constraints on the signal group, and the skew is constrained below 5ns [I have seen constraints of 1ns and 3ns. This skew threshold is related to the process and IO voltage] constraints include the soc terminal and the codec terminal. -----see picture 1
- Use high-frequency adifclk to sample the signal, and beat the signal with adifclk --- adjust the phase
- The rising edge of sclk changes the signal, and the falling edge samples data, so that there is enough sampling window ---- see Figure 4
Let T(sclk), T(fs) and T(sdo) be the delay time from adif TX to chip IO in TX master, or the delay time from chip IO to adif RX in Rx slave, respectively.
Among them, for the I2S interface that needs to output sclk+control signal+data, there are usually the following delay requirements
T(sclk) <= T(fs) <= T(sdo)------The premise of this constraint is that the setup, hold, and Tco are much smaller than the sclk cycle
Of course, if the rising edge of sclk is used to change the signal and the processing of the falling edge sampling signal, the above constraints do not need to be set.
Let's analyze the timing from the section of data from adif TX to chip IO:
NOTE : In the source signal in the figure below, both fs and sdo change on the rising edge, and the delay with the rising edge is very small. This delay is the internal delay Tco of the register, which is in line with the actual situation.
figure 1
It can be seen from the above figure that T(sclk), T(fs) and T(sdi) are quite different. The relationship between the three signals at the source is to use the rising edge of sclk to sample fs and sdo data, among which the first data of sdo is '1 'There is a beat interval between fs and fs; while at IO, when using sclk to sample fs and sdo, you will find that the first data of fs and sdo are two beats apart, and there is an obvious error, so try to restrain the skew of the signal during transmission. Ideally, the skew of the three signals is 0, and it must be correctly sampled at the receiving end.
figure 2
Figure 2 shows the situation of T(fs)< T(sclk) < T(sdo) in the case of rising edge conversion and rising edge sampling, although the skew between the three is not large [as long as T(sclk)>T(fs ) +Tco] , the first data of fs and sdo is different by 2 sclks.
Other situations that do not satisfy T(sclk) <= T(fs) <= T(sdo) are also prone to timing errors. The root cause is that Tco is too small, and the delay of T(fs) and T(sdo) will be small. is sampled in advance.
image 3
Figure 3 shows the timing diagram in the case of T(sclk) <= T(fs) <= T(sdo), and it is obvious that each signal is sampled on the correct edge.
Figure 4
Figure 4 shows the timing diagram of changing the signal at the source terminal on the rising edge, and sampling with the falling edge at the IO of the chip. T(fs) > T(sdo), but the data can still be sampled correctly. And it can be seen that compared with the falling edge, the left and right sides of the sampling window are much larger.
2. Inter-board latency of I2S/PCM
In the working mode of TX slave and Rx master, TX receives the ws/fs and sclk signals output by Rx and synchronizes them. This synchronization process requires TX two adifclk times, and the edge detection only changes the rear edge [that is, after the flip A signal with a pulse width is adifclk later, and then output sdo with the back edge of ws/fs and sclk, and sdo reaches RX after inter-board delay T(sdo), and at this time, ws/fs and ws/fs of RX and Sclk is used to sample sdo correctly, which requires that 3adifclk+T(sdo) should not exceed one sclk cycle. This can also be analyzed by drawing a timing diagram, which will not be repeated here.
In actual projects, since sclk is on the order of 100ns, adifclk is on the order of 10ns~0.xns, and T(sdo) is also in the range of tens of ns [ uncertain ], it is easy to achieve, and some projects do not Set constraints on latency.
If the distance between sdo and ws/fs on the RX master side is too far for more than 1 sclk, is there any design means to ensure that the audio reception is not affected?
At this time, RX will detect an error, such as the bit number of sdata is inconsistent with the left and right channels, or the bit number of the whole frame is different from the configuration value. At this time, an error is reported, and then the ws/fs on the Rx side is controlled to delay n sclks until the software detects no errors.