Table of contents
PWM output function
Pulse width modulation (PWM) is a method of digitally encoding the level of an analog signal. PWM technology is widely used in machinery, communication, power control and other fields, such as motor speed control, light brightness adjustment, DC-DC converter and signal modulation and other occasions.
PWM signal has two important parameters: period and duty cycle
•Period
The duration of a complete PWM waveform.
• Duty cycle (Duty)
The calculation formula of the duty ratio of the high level duration (Ton) to the period (Period) is as follows:
Duty=( Ton/Period)x 100%
The figure below shows PWM signals with three different duty cycles of 50%, 20% and 80%
In the figure above, the peak value of the voltage is 3.3 V, T represents the duration of the high level, and T represents the signal off time. The dotted line represents the average voltage corresponding to the PWM signal.
According to the calculation formula of average voltage: average voltage = peak value x duty cycle . We can calculate: the average voltage corresponding to the PWM signal with 50% duty cycle is 1.65V; the average voltage corresponding to the PWM signal with 2% duty cycle is 0.66V; The average voltage is 2.64V. Therefore, the basic principle that PWM signals can perform voltage regulation is that PWM signals with different duty ratios are equivalent to different average voltages.
1. Capture/Compare Channel
The capture/compare channel is responsible for the input capture function and the output compare function. Each timer can have up to 4 capture/compare channels, and each channel has a corresponding register for control and a corresponding GPIO pin as the input and output interface of the channel. The functional framework of the capture/compare channel is shown in the figure below.
The capture/compare channel consists of three modules: input capture unit, capture/compare register output compare unit.
1. Input capture unit
The input capture unit is used to capture external pulse signals, and the capture mode can be set as rising edge capture, falling edge capture and double edge capture. When a capture event occurs, the current count value of the counter is latched into the capture/compare register for the user to read, and a capture interrupt can be generated at the same time. The input capture is mainly used for signal measurement, which can measure parameters such as the period, frequency and duty cycle of the signal.
2. Capture/compare register
The capture/compare register TIMx_CCR is the most important register in the capture/compare channel. In the input capture mode, it is used to store the count value when a capture event occurs: in the output compare mode, it is used to store the preset comparison value. This register has a preload function and consists of a shadow register and a preload register. The preload function can be enabled or disabled by software.
3. Output comparison unit
The output compare unit is used for signal output. The timer achieves various outputs, such as PWM output, level inversion, single pulse output and forced output, by matching and comparing the preset comparison value with the count value of the counter. The preset comparison value is stored in the capture/compare register TIMx_CCR.
There are a few things to keep in mind when using capture/compare channels:
① Both the input capture function and the output comparison function are derived from the timing function. Therefore, the timer works in timing mode, the clock source is the internal clock CK_INT, and the prescaler clock CK_PSC of the time base unit is equal to the timing clock TIMx_CLK of the timer.
② Each timer has 1~4 independent capture/compare channels. Each channel has an independent input capture unit, capture/compare register and output compare unit, but shares the same time base unit.
③ Each capture/compare channel can be independently set as a capture channel (for input capture) or a compare channel (for output comparison), but only one of the two functions can be selected.
④ Each capture/comparison channel has a corresponding channel pin as the input/output interface of the channel, such as TIM_CHn (n indicates the channel number 1~4, the same below). These channel pins are multiplexed with GPIO pins. Users can select the function of GPIO pins as channel pins on the pin assignment diagram of CubeMX software.
2. PWM realization principle
To realize the output of PWM signal, three registers are needed: automatic reload register TIMx_ARR, capture/compare register TIMx_CCRn (n indicates channel number 1~4, the same below) and counter register TIMx_CNT, and output PWM through channel pin TIMx_CHn Signal.
For the convenience of expression, we record the content of the TIMX_ARR register as the automatic reload value ARR, the content of the TIMx_CCRn register as the capture/comparison value CCR, and the content of the counter register TIMx_CNT as the count value CNT. The output process of the entire PWM signal is shown in the figure below.
In the figure, we assume that the timer works in up-counting PWM mode, and when CNT<CCRx, it outputs 0, and when CNT>=CCRx outputs 1. Then you can get the above PWM schematic diagram: when the CNT value is less than CCRx, the IO outputs a low level (O0), when the CNT value is greater than or equal to CCRx, the IO outputs a high level (1), when the CNT reaches the ARR value time, reset to zero, then count up again, and cycle in turn. Changing the value of CCRx can change the duty cycle of PWM output, and changing the value of ARR can change the frequency of PWM output. This is the principle of PWM output.
According to the output process of the PWM signal, we can know that the automatic reload register TIMx_ARR is used to control the period capture/compare register of the PWM signal and the TIMX_CCRn is used to control the duty cycle of the PWM signal. To sum up, we can get the calculation formula of PWM signal period and duty cycle
T=(PSC+1) X(ARR+1)/TIMx_CLK
Duty=CCR/(ARR+1)x100%
A specific application example is introduced below. Assuming that the timing clock TIM_CLK of the timer is 100 MHz, it is required to output a PWM signal with a period of 1ms and a duty cycle of 47.5%, and the output waveform is shown in the figure below.
To generate such a PWM signal, first ensure a period of 1 ms. According to T=(PSC+1) X(ARR+1)/TIMx_CLK, we can set the prescaler coefficient PSC to 99, and the automatic reload value ARR to 999, thus obtaining a PWM period of 1ms. After determining the automatic reload value ARR, according to Duty=CCR/(ARR+1)x100%, the capture/comparison value CCR can be obtained as 475.
Each capture/compare channel of the timer has an independent input capture unit capture/compare register and output compare unit, which can output PWM signals respectively. For the same timer, since its multiple channels share the same auto-reload register, the content of the auto-reload register determines the period of the PWM signal. Therefore, for multiple channels of the same timer, PWM signals with different duty cycles but the same period can be output simultaneously. For example, we use channel 1 and channel 2 to output two PWM signals at the same time. Assume that the timing clock TIM_CLK is 100MHz, and the automatic reload value ARR is 999.
For channel 1, set TIMx_CCR1 to 475, and a PWM signal with a period of 1 ms and a duty cycle of 47.5% will be output on the channel pin CH1.
For channel 2, set TIMx_CCR2 to 700 to output a PWM signal with a period of 1ms and a duty cycle of 70% on the channel pin CH2.
The multi-channel PWM signal output of the same timer is shown in the figure below
