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Since the interface of SPI is relatively simple (only 4 wires are needed), the use is relatively Extensive, mainly used in EEPROM, FLASH,
Between the real-time clock, AD converter, and digital signal processor and digital signal decoder.
That is, an SPI Master communicates with a slave device, that is, the above-mentioned Flash, ADC, etc., through SPI.
For communication between the master and slave devices through SPI, first of all, it is necessary to ensure that the clock SCLK between the two must be consistent, and they must be discussed and matched.
Otherwise, normal communication will not be possible, that is, only when the consistency in timing is ensured can normal communication be performed.
The clock and phase in SPI here refer to the characteristics of the SCLk clock,
That is to ensure that the characteristics of the clocks of the master and slave devices are consistent, so as to ensure that the two can realize SPI communication normally.
The polarity and phase phase of SPI, the most common writing methods are CPOL and CPHA, but there are also some other writing methods, which are briefly summarized as follows:
(1) CKPOL (Clock Polarity) = CPOL = POL = Polarity = (clock) polarity
(2) CKPHA (Clock Phase) = CPHA = PHA = Phase = (clock) phase
(3) SCK=SCLK=SPI clock
( 4) Edge=Edge, that is, the moment when the clock level changes, that is, the rising edge (rising edge) or the falling edge (falling edge)
For one clock cycle, there are two edges, which are called:
(1) Leading edge = the previous edge = the first edge, for the starting voltage is 1,
Then when 1 becomes 0, the starting voltage is 0, then 0 becomes 1;
(2) Trailing edge = the next edge = the second edge, for the starting voltage is 1,
Then it is when 0 becomes 1 (that is, after the first 1 becomes 0, the subsequent 0 may become 1),
For the starting voltage is 0, then it is when 1 becomes 0;
This blog post uses the following usage:
Polarity = CPOL
phase = CPHA
SCLK = clock
The first edge and the second edge
CPOL and CPHA can be 0 or 1 respectively, and the corresponding four combinations are:
Details below.
CPOL polarity
Firstly, what is the idle time of the SCLK clock, which is the state of SCLK before and after sending 8 bits of data,
Corresponding to this, when SCLK is sending data, it is the time of normal work and the moment of effective active.
Its simplified English explanation is: Clock Polarity = IDLE state of SCK.
The CPOL of SPI indicates that when SCLK is idle, its level value is low level 0 or high level 1:
CPOL=0, the level when the clock is idle is low level, so when SCLK is valid , is high level, which is the so-called active-high;
CPOL=1, the level when the clock is idle is high level, so when SCLK is valid, it is low level, which is the so-called active-low;
As can be seen from the above figure, the SCK waveform of (CPOL=0) has (transmission) 8 pulses, and remains in the [low level state] before and after the pulse transmission.
The state at this time is the idle state or invalid state of the clock, because there is no pulse at this time, and there will be no data transmission.
In the same way, in the diagram of (CPOL=)1, SCK is kept [high level] when the clock is idle or inactive.
CPHA phase
First, let me explain that capture strobe = latch = read = sample, all of which represent data sampling and the moment when the data is valid.
Phase, corresponding to which edge (edge) the data sampling is on, whether it is the first edge or the second edge,
0 corresponds to the first edge, 1 corresponds to the second edge. for:
CPHA=0 means the first edge:
for CPOL=0, the idle time is low level, and the first edge changes from low to high, so it is a rising edge;
for CPOL=1, the idle time is high level Flat, the first edge is from high to low, so it is a falling edge;
CPHA=1, means the second edge:
for CPOL=0, the idle time is low level, and the second edge changes from high to low, so it is a falling edge;
for CPOL=1, the idle time is high power Flat, the first edge is from low to high, so it is a rising edge;
We look at the above figure and find that the data SI corresponds to the first clock edge of SCK,
Look carefully, the data is stable at the first clock edge of SCK [data is sampled and captured],
Change on the next edge [SCK falling edge data change] So we conclude:
This series of FLASH is [data is sampled and captured at the first clock edge]
Or [data is captured at the start edge of SPCK and changed at the next edge of SPCK]
How to judge CPOL and CPHA
If the initial SCLK level is 0, then CPOL=0, if it is 1, then CPOL=1,
Then look at the data sampling time, that is, the position corresponding to the middle of the rectangular area of the data on the sequence diagram data line,
Corresponding to the position of the SCLK clock above, it corresponds to the first edge or the second edge, that is, CPHA is 0 or 1.
(Whether it corresponds to a rising edge or a falling edge depends on the value of the corresponding CPOL to determine).
(1) How to judge CPOL: The voltage of SCLK when it is idle is 0 or 1, which determines whether CPOL is 0 or 1; (2) How to judge
CPHA: The level of SCLK corresponding to the data sampling time is the first The edge is still the second edge, corresponding to whether CPHA is 0 or 1.
Finally, let's take a look at the CPOL and CPHA of the SPI of the S3C2440. Combined with the theoretical knowledge mentioned above, the following figure is easy to understand!
Here, explain more about CKP and CKE that may be encountered, which are the words in Microchip's PIC series chips.
(1) CKP is Clock Polarity Select, that is, polarity = CPOL:
CKP, although the name is different from CPOL, both refer to the selection of the clock phase, and the definition is the same:
CKP: Clock Polarity Select bit
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
So not much to explain.
(2) CKE is Clock Edge Select, that is, phase = CPHA:
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
meaning is
1 = (data) transfer occurs at the moment the clock transitions from the active state to the idle state
0 = (data) transfer occurs at the moment the clock transitions from the idle state to the active state
Among them, the moment of data transmission, that is, the "moment of data transmit transmission" marked in the figure, obviously,
The moment is the junction between one clock and the next clock, corresponding to whether it is a rising edge or a falling edge,
Both are opposite to the edge direction of the CPHA=data sampling moment we mentioned earlier.
Therefore, CKE here is exactly the opposite of CPHA.
Therefore, the meanings of the values corresponding to CKP and CKE are:
When CKP = 0: CKE=1 => Data transmitted on rising edge of SCK, CKE=0 => Data transmitted on falling edge of SCK
When CKP = 1: CKE=1 => Data transmitted on falling edge of SCK, CKE=0 => Data transmitted on rising edge of SCK
STM32F4 SPI Data clock timing diagram
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register.
The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
This bit affects both master and slave modes.
If CPOL is reset, the SCK pin has a low-level idle state.
If CPOL is set, the SCK pin has a high-level idle state.
If the CPHA (clock phase) bit is set, the second edge on the SCK pin is the MSBit capture strobe.
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set)
Data are latched on the occurrence of the second clock transition.
If the CPHA bit is reset, the first edge on the SCK pin is the MSBit capture strobe.
(falling edge if CPOL bit is set, rising edge if CPOL bit is reset)
Data are latched on the occurrence of the first clock transition.
The combination of the CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge.
Figure 248, shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram
where the SCK pin, the MISO pin, the MOSI pin are directly connected
between the master and the slave device.
Note:
Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
Master and slave must be programmed with the same timing mode.
The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register
(by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
The Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register,
and determines the data length during transmission/reception.
SPI Transfer Modes
SPI interface allows to transmit and receive data simultaneously on two lines (MOSI and MISO).
Clock polarity (CPOL) and clock phase (CPHA) are the main parameters
that define a clock format to be used by the SPI bus.
Depending on CPOL parameter, SPI clock may be inverted or non-inverted.
CPHA parameter is used to shift the sampling phase.
If CPHA=0 the data are sampled on the leading (first) clock edge.
If CPHA=1 the data are sampled on the trailing (second) clock edge,
regardless of whether that clock edge is rising or falling.
CPOL=0, CPHA=0
The data must be available before the first clock signal rising.
The clock idle state is zero.
The data on MISO and MOSI lines must be stable while the clock is high and can be changed when the clock is low.
The data is captured on the clock’s low-to-high transition and propagated on high-to-low clock transition.
CPOL=0, CPHA=1
The first clock signal rising can be used to prepare the data.
The clock idle state is zero.
The data on MISO and MOSI lines must be stable while the clock is low and can be changed when the clock is high.
The data is captured on the clock’s high-to-low transition and propagated on low-to-high clock transition.
CPOL=1, CPHA=0
The data must be available before the first clock signal falling.
The clock idle state is one.
The data on MISO and MOSI lines must be stable while the clock is low and can be changed when the clock is high.
The data is captured on the clock’s high-to-low transition and propagated on low-to-high clock transition.
CPOL=1, CPHA=1
The first clock signal falling can be used to prepare the data.
The clock idle state is one.
The data on MISO and MOSI lines must be stable while the clock is high and can be changed when the clock is low.
The data is captured on the clock’s low-to-high transition and propagated on high-to-low clock transition.
SPI Modes and Timing.
Introduction
In a lot of cases, when using SPI, we do need to use “SPI_Init_Advanced”.
It has a number of parameters. Here the parameters regarding the SPI “mode” are described. The “mode” consists of
The SPI clock (SCK) polarity (parameter clock_idle)
The PIC SPI data out transmit edge (parameter edge)
in
procedure SPIx_Init_Advanced(…, data_sample, clock_idle, edge: word);
The “data_sample” parameter does not belong to the actual “SPI mode”, it is an extra feature of the MCU, see here.
The SPI “Modes”
SPI knows 4 “standard” modes, reflecting the SCK’s polarity (CPOL) and the SCK’s phase (CPHA).
The definition is:
The meaning is:
CPOL:
0 = Clock Idle low level
1 = Clock Idle high level
CPHA:
0 = SDO transmit edge (*) active to idle
1 = SDO transmit edge idle to active
(*): the transmit edge is the clock edge at which the SDO level changes
In a timing diagram this looks like(only one clock pulse shown here):
The Transmit edge is the clock edge at which the SPI output data changes,
the Sampling edge is the clock edge at which the sampling of the SPI input data takes place.
The sampling edge is normally the opposite one of the transmit edge, but see also here.
SPI and PIC/ dsPIC
The PIC MCU supports a 4 SPI modes, but the MCU registers involved are named differently and behave differently.
The 2 MCU registers are CKP (Clock Polarity) and CKE (Clock edge).
The relation between those 2 registers and the SPI modes is:
As you can see, CKP behaves the same as CPOL, CKE is the inverse of CPHA.
This means that a simple “SPI_Set_mode” looks like this:
procedure Set_SPI_mode(CPOL_, CPHA_: byte);
// The 2 paremeters are:
// CPOL: SPI clock polarity: 0 = Clock Idle LOW; 1 = Clock Idle HIGH
// CPHA: SPI clock Phase: 0 = Transmit edge active to idle; 1 = Transmit edge Idle to active
begin
CKP_bit := CPOL_;
CKE_bit := (CPHA_ xor 1) and 1; // invert bit zero
end;
Above routine can e.g. used after a usage of an mE SPIx_Init… routine to (re)set the SPI mode.
The mE SPI library usage
In the mE SPI library the “SPI mode” is set by 2 parameters of the “SPIx_Init_Advanced” function.
The the parameters for PIC are : “clock_idle” and “transmit_edge”
The the parameters for dsPIC are: “clock_idle” and “edge”
Important: in both cases the last parameter (“transmit edge” or “edge” parameter) is
NOT the transmit edge, but the other one, called the “Sampling edge”,
see here. As you can see the name of the PIC parameter is wrong (it says “transmit_edge”).
Furthermore the constant values used to give the parameters their values are:
For PIC:
CPK: _SPI_CLK_IDLE_LOW and _SPI_CLK_IDLE_HIGH
CPE: _SPI_LOW_2_HIGH, _SPI_HIGH_2_LOW (**)
For dsPIC:
CPK: _SPI_CLK_IDLE_LOW and _SPI_CLK_IDLE_HIGH
CPE: _SPI_ACTIVE_2_IDLE, _SPI_IDLE_2_ACTIVE (**)
(**) Again: the “edge” is the “Sampling Edge”, not the “Transmit Edge”, see here.
Deriving the parameters from the device’s “SPI mode”
The easiest way is using the “SPI mode” if known, the hardest is deriving the parameters from the device’s timing diagram.
The table below gives the relationship between an SPI device’s “SPI mode” and the parameter values to use with “SPIx_Init_Advanced”:
SPI MODE clock idle parameter Edge parameter = the “Sampling” edge
0,0 _SPI_CLK_IDLE_LOW _SPI_LOW_2_HIGH (pic) : _SPI_IDLE_2_ACTIVE (dsPIC)
0,1 _SPI_CLK_IDLE_LOW _SPI_HIGH_2_LOW (pic) : _SPI_ACTIVE_TO_IDLE (dsPIC)
1,0 _SPI_CLK_IDLE_HIGH _SPI_HIGH_2_LOW (pic) : _SPI_IDLE_TO_ACTIVE (dsPIC)
1,1 _SPI_CLK_IDLE_HIGH _SPI_LOW_2_HIGH (pic) : _SPI_ACTIVE_TO_IDLE (dsPIC)
Important:
In mikroPascal the parameter “edge” represents the clock edge where in input data is sampled,
not the “transmit edge” (the clock edge at which the SDO data is changed).
The parameter “data sample” is not included in the “SPI mode”,
but usually “_SPI_DATA_SAMPLE_MIDDLE” will do fine, see however also here.
Defining parameters from the device’s timing diagram
This manner has to be applied if the “SPI mode” of the device at hand is not (explicitely) defined.
To find out the necessary values of the parameters we have to look to the device’s SPI timing diagram we want to handle:
Keep in mind that in the “device” diagram the “device” timing is shown.
For the PIC timing input and output should be interchanged (which was already done in the above diagram,
it shows the timing from the PIC’s perspective).
- The “clock_idle” parameter
See 1 in the diagram. The level wanted is the SCK level at the moment notCS changes. In the diagram this level is zero, so: theclock idle is low.
This means also that (again in our case) the clock active level is high.
- The “edge” parameter
See 2 in the diagram. The edge wanted is the one in the middle between 2 PIC output (PIC SO) datachanges (two “transmit” edges, represented by “x” in the timing diagram).
In our case we see that it is the edge from low to high, or from idle to active.
The “data_sample” parameter
The data_sample parameter is not defined in the SPI mode, it is an extra feature of the MCU.
Normally the “Sampling edge” (see here) is the opposite one of the “transmit edge”.
This is achieved by setting the “data_sample” parameter to the value “_SPI_DATA_SAMPLE_MIDDLE”.
The sampling moment can however be shifted to the same moment as the transmit edge
by setting the “data_sample” parameter to the value “_SPI_DATA_SAMPLE_END” value, see here).
How to define which one to use:
See 3 in the above diagram.
First define the “data output time”, represented by an x in the timing diagram.
It is the time from one PIC output data (PIC SO) change to the next.
Now compare the device data out (SO = PIC SI) with the “data output time”.
The data_sample value we have is the best moment in the “data output time”
the PIC should take a sample of its input data (the device output data).
In our case, the middle of the “data output time” seems to be the most appropriate (at the end would be not bad either).
Info
a. Timing diagram (derived and modified from Mchp datasheet)
This is the (master) timing diagram with the terms explained: