Special episode 13: Using ADS for tolerance analysis (Monte Carlo analysis, sensitivity analysis, yield analysis, yield optimization), taking bandpass filter design as an example

Special episode 13: Using ADS for tolerance analysis (Monte Carlo analysis, sensitivity analysis, yield analysis, yield optimization), taking bandpass filter design as an example

Download

https://download.csdn.net/download/weixin_44584198/88210327

technical background

Tolerance analysis is one of the most advanced technologies in current electronic reliability design, and represents an important development direction of electronic reliability design. Monte Carlo analysis is a major technique of tolerance analysis. It is to analyze whether the circuit performance of the circuit device will exceed the specification requirements of the circuit performance under the error condition.

To put it simply, most of the devices in the circuit, such as capacitors and resistors, will have a certain error (for example, 5%), but how will the combination of these errors affect the final performance? As we all know, this is a small probability problem, but for products shipped in batches and volumes, such errors need to be specially analyzed. Generally, large companies or products with high quality requirements will be required to make tolerances when designing Analysis, the method of tolerance analysis using ADS is introduced here.

1. Design indicators

Assuming that we need to design a bandpass filter here, the main performance indicators of the filter are as follows:
Cutoff frequency 1: 8MHz
passband 1: 9.5MHz
passband 2: 10.5MHz
Cutoff frequency 2: 12MHz
passband Ripple: <0.5 dB
stopband attenuation: >20dB

Assuming that the error of the lumped parameter components used in the design is 5%, in fact, for most common SMT devices, this 5% error is very reasonable.

2. Bandpass filter design

First design a bandpass filter according to the requirements, create a new schematic diagram and name it BasicFilter, find the Filter DG - ALL option in the library and open it: find the

bandpass filter design module and insert it into the schematic diagram (DT):

For the inserted components, set their parameters reasonably, and the specific requirements should be based on the above design indicators:

insert related simulation controls, mainly S parameter controls, and set their simulation frequency: select

DesginGuide in the menu bar, find the Filter option and click Open:

Select the first Filter Control Window option, click OK:

Select the second tab, Filter Assistant (Overview when it is opened by default), and click the Design button:

After waiting for a few seconds, the design is completed, although it cannot be seen on the surface What happened, but click the button to go deep into the device to check:

you can find that there are already relevant resistors and capacitors in the circuit:

go back to the previous layer and click the simulation button, you can see the simulation results under ideal conditions as follows, and the performance seems to be good:

3. Tolerance analysis (Monte Carlo analysis is used here)

Create a new schematic diagram, named MonteCarlo_Filter, put the previously designed circuit into it and insert the relevant S-parameter controls:

find the relevant simulation controls (MC, Monte Carlo abbreviation) from the Optim/Stat/DOE option, after insertion, you need Set the relevant parameters of the Monte Carlo control as follows:

Among them, Numlter is set to 100, which means a total of 100 analyzes. Before starting the simulation, you need to set the error range of the device. Double-click the device and click the Tune/Opt/Stat/DOE Setup button: enable Statistics and set the error 5%

:

set After the completion, click the simulation to view the results. It can be seen that the device error has a great influence on the final performance of the circuit, and the frequency offset and matching performance fluctuate, but the specific performance is not clear in the figure: build the following observation window to observe the S11 and S11 at

10MHz S21 performance, found that the Monte Carlo analysis shows that the performance is poor in the 33rd and 74th experiments, at this time at 10MHz, S11 is greater than -1dB, S21 is less than -6dB, the circuit function is almost completely lost: move the mouse

slider , check the 33rd experiment results and the corresponding resistance and capacitance values:

It can be seen that the circuit performance may be very problematic in actual mass production.

4. Yield analysis and yield optimization

Find the relevant simulation controls (YIELD SPEC and YIELD controls) from the Optim/Stat/DOE option, notice that the original Monte Carlo analysis controls are commented out, and the values ​​​​of the YIELD SPEC and YIELD controls should be set reasonably. Observe the YIELD below SPEC control, here is set to a device with S11 less than -10dB at 9.96MHz to 10.1MHz is a good device, in fact, this requirement is already very low:

run the simulation, it can be seen that in the case of a device error of 5%, the entire bandpass filter The device yield rate is 20%. This is very scary, so there should be enough margin in the actual design. For example, if I set the passband range from 8MHz to 12MHz, the S11 yield performance of the device may be much better: the following is a

good To optimize the yield, find the relevant simulation control (YIELD ORTIM... control) from the Optim/Stat/DOE option, and insert it as shown below. It can be seen that the number of optimizations for the set yield is 100: before running the yield optimization, you need to

set Device Optim, set the optimization range of the device to 50% here:

Click the simulation to run the yield optimization. It is worth noting that the results of each run of the yield test may not be consistent, because in fact this is a random experiment. The final result shows that the initial yield rate is 12.8%, and it is 27% after optimization. It seems that the error here is relatively large. In fact, it can be converged by increasing the number of experiments, but this operation is relatively slow, so we will not discuss it here. Specifically demonstrated:

For the optimized results, the relevant options in Simulation can be updated, as follows:

5. Sensitivity analysis

Comment out the controls related to yield analysis, find the relevant sensitivity analysis controls from the Optim/Stat/DOE option, insert and as shown below: Among them,

Goal needs to be specially set, and what is measured here is the S11<-10dB requirement of the circuit at 10MHz Under the lower sensitivity, run the simulation:

It can be seen that C1, C3, L1, and L3 contribute greatly to the S11 performance of the circuit.

6 Conclusion

There is a margin in the design to ensure nothing goes wrong!