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This article only represents my personal point of view. It can be regarded as a personal summary. I believe that this article will continue to improve with the deepening of learning.
1、UART
1. Synchronous and asynchronous
First of all, let's look at the difference between the two concepts, such as opening the cube
Their full names are:
- UART Universal Asynchronous Receiver Transmitter
- USART Universal Synchronous/Asynchronous Receiver/Transmitter
It can be seen that the USART can have a synchronization function. The synchronization here is to increase the clock line, which is reflected in the smart card in the configuration of the stm32 cube. This synchronization communication function can use the USART as an SPI. For example, use the USART to Drive SPI devices.
The following is the configuration of UART, compared to the part without smart card, but we generally use the serial port as an asynchronous serial port, so don’t pay special attention here
asynchronous synchronous
- Asynchronous: The sender has to wait for the receiver to send a response before continuing to communicate, which is a blocking communication method
- Synchronization: It does not matter whether the receiver responds, it is a non-blocking communication method
From this point of view, IIC and SPI are synchronous communication (Determined by the clock, a synchronous bit stream that is continuously sent and received continuously), UART is asynchronous communication, but although UART does not need to respond, but he can send characters at any time, so he needs start bit and stop bit , so as to tell others when to start and when to end, so that the receiver can Data is received correctly.
2. Hardware layer
The RS232 standard is generally used here. RS232 is an old standard. It specifies the purpose of the signal, the communication interface and the level standard of the signal. The commonly used interface is generally the DB9 interface. The difference between RS232 and the current serial port lies in one Level standard, below is the schematic from the wildfire stm32 tutorial.
Their level standards are as follows:
The standard DB9 interface is as follows (Pay attention to the swap of RX and TX here), now generally only use three signal lines RXD, TXD and GND to directly transmit data signals.
3. Protocol layer
As mentioned earlier, it is the way of protocol transmission, which needs to be started and stopped. The transmitted data packets are generally:
Start bit-body data-check stop data
The following are some important parameter descriptions:
- Baud rate : Because there is no clock signal, if you want to receive data correctly, you need to agree on the communication baud rate, which can be understood as the communication rate. The meaning of baud rate is the number of bits per second, for example, 115200 is 115200 bits of data are transmitted per second.
- Start and Stop Signals : Each packet begins with a start signal (logic 0) start to stop signal end (0.5, 1, 1.5 times of logic 1 to represent）
- Valid data : 8 bits or 9 bits, the transmitted data is 9 bits, but whether the 9th bit is valid needs to be determined
- Data verification : This is also optional, and it is performed to prevent errors caused by external interference. Specifically, it includes odd parity (odd), even parity (even), 0 parity (space), 1 parity (mark ) There are several ways of no parity
If we need to read the data of the serial port, we need to read the data register. In stm32, it is the DR register. This is a 16-bit register, generally the lower 9 bits are valid (That is, the effective data length mentioned above is generally 8 or 9 bits., whether it is valid here is determined by the M bit of the control register CR1, 8 bits when it is 0, and 9 bits when it is 1)
Since the same DR register is a data register, there are two cases of sending and receiving data, so there are also two parts, namely:
- TDR: Dedicated Send
- RDR: dedicated reception
In the actual sending process, the content of the TDR is first sent to the shift register, and then the shift register sends the data bit by bit.
Then in the supplementary description, the CR1 register mentioned above, the CR1 register is the control register, and the content of the control includes
- Data length
- Whether to DMA
- sender, receiver
- Wake-up unit, interrupt control (you need to write 1 to CR1 register TE to enable UART before using the serial port)
In the process of sending, the low bit comes first, and the high bit comes after. The specific sending process is: first send an idle frame (here is a high level of data frame length), and then start writing the data to be sent to the DR register. After writing the last data, wait for the TC bit of the UART status register to be 1, indicating that the transmission is complete. If the TCIE of CR1 is set to 1 during this process, an interrupt will be generated. Here are some very important flag bits:
- TE: send
- TXE: transmit register is empty
- TC: send completed
- TXIE: Transmit Complete Interrupt Enable
If it is a receiver, it is roughly similar to the above part, except that some names have been changed.
2、IIC
Let's talk about the IIC protocol. In fact, I have written articles and records in this regard before, but that is partial to application. This article here is considered partial theory!
1. Features
IIC has two lines, SDA is the data input and output line, and SCL is the clock signal line, because there is a clock to synchronize the signal, so IIC is synchronous communication.
A major feature of iic is that it is a multi-master and multi-slave bus communication method. There can be multiple masters on one iic bus, and there can also be multiple slaves, which is not available in many other buses. At the same time, iic has high data requirements, because every time he sends a data, he needs a response (Send a non-acknowledgement NACK when it is about to end）。
2. Hardware layer
The bus on the hardware layer is the best layout, but just pay attention to connecting a pull-up resistor, because it is necessary to ensure that the idle state is a pull-up state.
3. Protocol layer
The protocol layer is shown below, and the data is written below (Each data must be followed by a response, and finally a non-response)
Below is the read data (Each data must be followed by a response, and finally a non-response)
The overall words are roughly as follows: (Each data must be followed by a response, and finally a non-response)
start signal and acknowledge signal (SCL is high, SDA falling edge is the start, SCL is high, SDA rising edge is the end)
response signal
Then how should the data be read, it is very simple in one sentence:SDA performs data transmission every clock cycle of SCL, and one bit of data is transmitted every clock cycle
The clock cycle here can be roughly understood as a square wave, which is constantly changing up and down. This is only one cycle, and then the data is not read throughout the clock cycle. It should be noted here that it is only read when SCL is high. Fetching data can also be understood as when SCL is high level, the data is valid. At this time, read the level state of SDA. If SDA is high level, it is 1, otherwise it is 0. When SDA is low level, this time SDA can perform level conversion. For example, if it is converted at this time, it will read 10. If it is not converted, it will be 11. In this way, a total of eight times is performed, and one byte of data transmission is completed!
3、SPI
The following is a summary of SPI. I also have related articles about this. You can check my previous articles. It is still the same, and it is more application-oriented. Here is an interpretation of the theory.
1. Features
The characteristics of SPI are high-speed, full-duplex, synchronous communication. SPI is different from iic. On the same bus, there can only be one SPI master at most, and there can be multiple slave devices, but there must not be multiple masters. SPI read All writes are initiated by the master device. When there are multiple slaves, the selection of the slave by the master is determined by the chip select signal of each slave.
2. Hardware layer
The layout of the bus on the hardware layer is the best. Here, pay attention to the chip select signal.
3. Protocol layer
There is a picture below depicting the SPI communication protocol, which is quite ugly.
To be honest, SPI is a very easy protocol. It is quite complicated after being messed up like this. I have drawn a picture below. I believe it will be easier to understand the SPI protocol. Is it better to look at the data or the clock? Here
and The IIC has the same clock line, but there is an extra data line, yes, why is it a full-duplex bus, synchronous transmission, then the data transmission still captures the data on the data line in the clock cycle, then That's it.
Another point of SPI is that it has two more things, which makes this process a little bit more complicated. It is really a little bit more complicated. These two are clock phase and polarity.
Because of these two things, SPI can have four working modes, the following two things (CPOL is the clock polarity, CPHA is the clock phase) to introduce the role of:
- CPOL=0: data is valid when SCLK=1
- CPOL=1: Data is valid when SCLK=0
- CPHA=0: data sampling on the first edge
- CPHA=1: Data is sampled on the second edge and sent on the first edge
What does it mean to be effective here:
- The rising edge of the first edge and the falling edge of the second edge are valid for SCLK=1
- The falling edge of the first edge and the rising edge of the second edge are valid for SCLK=0