It's not just a few questions, but it needs to be able to map to the actual basic cells.
1: Write an edge, which is basically a clock, and reset the register synchronously;
2: Write 2 edges, one clk, one reset (0) or set (1). Reset registers with asynchronous;
3: Write 3 edges, one clk, one reset, and one set. Use a register with asynchronous set/reset at the same time (this is rarely used, ASIC can have a corresponding basic cell); at this time, except for the first clock edge, the other two edges are asynchronous (set/reset)
The standard writing method recommends a maximum of two edge triggers in the design, the syntax itself is supported, and there is no problem with the simulation, but considering the underlying unit (FPGA/ASIC), it is not recommended to write this way, which will cause problems in the synthesis mapping!
Recommend an in-depth introductory course on digital IC/fpga design: http://bbs.eetop.cn/thread-854132-1-2.html
(the above is from an author of eetop)
The following is reproduced:
The design that satisfies the Verilog grammar may not be able to be synthesized, because Verilog essentially describes hardware, so the thinking should be changed. Only based on the actual circuit instead of grammar, the designed function can be synthesized and implemented; hardware description language: Verilog
is essentially It is a hardware description, and the essence of the design is still the hardware design. So one must always remember that you are using register transfer language (RTL) to synthesize inference hardware, with the circuit in mind. Verilog HDL can do almost anything, but a description that satisfies the syntax requirements may not be able to be synthesized. Because when designing for synthesis, the code must map to the available hardware on the FPGA.
Flip-flops and the always@() statement:
A very common device in FPGAs is a flip-flop; a flip-flop is a device that has a clock and is only sensitive to one edge of that clock. Therefore, synthesis tools can only map to this device when the sensitivity list is of the form always@(posedge clk). We have variants of flip-flops, flip-flops that can do asynchronous preset/clear, that will map to an always@(posedge clk or <posedge/negedge>rst) statement.
That is, there are only two kinds of flip-flops in reality: one is only sensitive to one clock edge; the other is sensitive to one clock edge and has an asynchronous control terminal
; There is a clock edge item; although the syntax of the double clock edge trigger is correct, it cannot be synthesized; because there is no such element in reality, although the simulation is correct, this problem will be exposed when it is synthesized into the corresponding circuit;
Such as the implementation of the odd frequency division circuit before: the design of the odd-even frequency division circuit
Realization 1: frequency division on the rising edge, shifting on the falling edge, and the phase-or mode of the latter
two Realization 2: double-edge counting inversion method (actually, it cannot be synthesized)
two Both methods have double-edge triggering problems, pay attention to whether the Verilog description can be synthesized;
Reference :
Thanks to the great master Reborn Lee for his wonderful explanation in the blog, the original text is as follows:
[Verilog] Why can't the sensitive source of always@() be triggered by both edges? Why can't dual clock trigger?
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The design that satisfies the Verilog grammar may not be able to be synthesized, because Verilog essentially describes hardware, so the thinking should be changed. Only based on the actual circuit instead of grammar, the designed function can be synthesized and implemented; hardware description language: Verilog
is essentially It is a hardware description, and the essence of the design is still the hardware design. So one must always remember that you are using register transfer language (RTL) to synthesize inference hardware, with the circuit in mind. Verilog HDL can do almost anything, but a description that satisfies the syntax requirements may not be able to be synthesized. Because when designing for synthesis, the code must map to the available hardware on the FPGA.
Flip-flops and the always@() statement:
A very common device in FPGAs is a flip-flop; a flip-flop is a device that has a clock and is only sensitive to one edge of that clock. Therefore, synthesis tools can only map to this device when the sensitivity list is of the form always@(posedge clk). We have variants of flip-flops, flip-flops that can do asynchronous preset/clear, that will map to an always@(posedge clk or <posedge/negedge>rst) statement.
That is, there are only two kinds of flip-flops in reality: one is only sensitive to one clock edge; the other is sensitive to one clock edge and has an asynchronous control terminal
; There is a clock edge item; although the syntax of the double clock edge trigger is correct, it cannot be synthesized; because there is no such element in reality, although the simulation is correct, this problem will be exposed when it is synthesized into the corresponding circuit;
Such as the implementation of the odd frequency division circuit before: the design of the odd-even frequency division circuit
Realization 1: frequency division on the rising edge, shifting on the falling edge, and the phase-or mode of the latter
two Realization 2: double-edge counting inversion method (actually, it cannot be synthesized)
two Both methods have double-edge triggering problems, pay attention to whether the Verilog description can be synthesized;
Reference :
Thanks to the great master Reborn Lee for his wonderful explanation in the blog, the original text is as follows:
[Verilog] Why can't the sensitive source of always@() be triggered by both edges? Why can't dual clock trigger?