11. LNA design of ADS use record
Based on ADS2022
The reference book is Mr. Lu Yifeng's ADS RF circuit design and simulation study notes
Pre-tutorials:
01. New project of ADS use records 02.
Import of ADS use records Import of various simulation models 03.
Use of DC simulation controllers of ADS use
records 04. Use of S simulation controllers of ADS use records & elliptic low-pass filter design 05.
Lumped parameter matching of ADS use records 06.
Distributed parameter matching of ADS use records 07. Matching
Q value of ADS use records-broadband and narrowband
08. Low-pass filter design and optimization of ADS use records
09. Filter of ADS use records Automatic design 10.
Design high and low impedance filters using ADS records (including layout simulation)
0. The resources of this project
ADS model and data sheet of ATF54143 -based LNA design engineering ATF54143
1. Design indicators
It is required that the center frequency of the LNA work is 433Mhz,
the gain requirement is Gain>15db,
the noise Fmin<0.5db
2. FET data sheet reading
This design uses ATF54143 as the core device. You should first read its data sheet
to see some extreme performance. This part is not so important, but it can provide a lot of information when selecting the device: look at the official
recommended design. Generally,
you need to design the circuit structure according to the official recommended design: the last is the most important data chart environment.
It can be seen from the above figure that the best noise performance can be achieved when Vds=3V and Id is about 20mA, and the gain is greater than 16db. In this design, Vds=3V, Id=20mA can be used as design parameters.
3. Import zap and observe the device characteristics to determine the static working point
从官网下载并得到ATF54143的相关模型，下载得到的文件为zap格式，需要使用ADS进行导入，点击菜单栏的File菜单并找到unarchive选项，点击后选中刚刚下载得到的zap文件，选择解压位置解压：
解压后是一个新的工作空间，如下所示：
下面使用直流扫描观察ATF54143的器件特性，新建原理图并命名为LNA_DC_TEST:
在器件栏搜索并找到器件，插入至原理图：
下面插入模板，在insert中找到Template并点击，选择模板DC_FET_T并打开插入至原理图：
插入链接相关连线，如下所示：
下面修改FET Curve Tracer的设置，双击控件，修改参数，由上述数据手册得器件Vgs范围为0.4-0.8V左右，Vds为1-5V左右，按照上述要求设置控件：
After the setting is complete, click Simulation to get the result. It is observed that when Vds=3V, Ids=22mA, and Vgs=0.489V, it is more in line with this design. I think that the gain is high and the noise figure is small at this time (you can compare it with the previous data sheet):
4. Use the ADS tool to automatically design the FET bias circuit
The new schematic is named LNA_Bias:
Find Transistor Bias in the toolbar in the new schematic and insert the FET control (the second in the first row):
Insert the ATF54143 device and connect the relevant pins (the power supply voltage is 5V, and the other pins can be connected): Double-
click the DA_FETBias control and set the parameters reasonably. The parameters are consistent with the above design parameters (Vt and K can not be written):
Select the Amplifier option in DesignGuide to open
Select Transistor Bias Utility in Tools and open:
Select the Resistive Networks window:
Modify the following options and click design:
Select DC1 in the pop-up window:
after a period of time, the automatic design will end, observe the circuit: create a
new schematic diagram, name it LNA_Main, copy the above voltage divider circuit and place the device (select integer values for resistors and capacitors): click the simulation button After the simulation is completed, click Annotate Voltage and Annotate
Pin Current in the menu bar, and the node voltage and node current will be displayed on the schematic diagram:
Observe the relevant parameters at this time, the voltage and current meet the design requirements, the actual Id=20.5mA, Vgs=0.485V, Vds=3.15V. At this point, the design of the bias circuit is completed.
5. Stability analysis
In order to ensure that the system operates stably and does not explode, a stability analysis is required. Stability analysis requires S-parameter analysis. Here, the newly created schematic is named LNA_MAIN_S:
copy the above DC analysis circuit to the new circuit diagram, delete the DC control and add the S-parameter simulation control, and set the S-parameter sweep range reasonably:
Add ports, DC blocking capacitors and DC-Feed components to the output and input terminals. The DC blocking capacitors and DC-Feed components are in the Lumped Components device column (DC-Feed components can be understood as AC blocking inductors, which are used to block AC signals to ensure stability):
Search for the stability analysis control stabfact in the toolbar and add:
Search for the maximum gain analysis control and add:
The final circuit diagram is as follows:
Carry out the analysis, and draw the following two parameters (maximum gain and stability) after completion:
the analysis and obtained data graph is as follows, at 433Mhz, the stability is 0.17, and the maximum gain is 27db. Therefore, the circuit is not absolutely stable and needs to be modified:
The modification methods are:
1. Add feedback, add capacitor resistance to the drain, add a lossy network to the gate, etc., so as to reduce the loop gain to prevent oscillation, but this method will worsen the noise
2. Increase the inductance at the source level.
Here, the method of adding inductance to the source is selected, and the circuit diagram is as follows (after adding the inductance, set the inductance value to l1nH, l1 is a variable and set variable tuning):
Next, perform variable tuning, click the tuning icon:
gradually modify the value of variable l1, and observe the trend of the curve:
It is found that the stability is greater than 1 when the inductance value is 26nH, which meets the design requirements, and the gain is 16db at this time:
This completes the stability analysis.
6. Stability analysis and impedance analysis
Create a new schematic diagram and find the Design Guide's Amplifier option in the schematic diagram:
After opening, select the following options:
Click OK and unzip, a new schematic diagram will appear:
copy our circuit diagram in, delete unnecessary components:
Set the S parameters reasonably and start the simulation, click the simulation button, and the result picture will appear:
adjust the adjustment window in the center to 433M, observe the state of the system at 433M: observe the
relevant parameters at this time, the stability coefficient is about 1.3, which meets the requirements: the
link gain is 12.5DB does not meet the requirements:
the following is the tuning in this schematic diagram, click the tuning button, and found that when the source-level grounding inductance is 10nH, the gain is 19db, and the stability is 1.094. The system is stable and meets the design requirements:
In the radio frequency circuit, the inductance is relatively small, so it is replaced by a transmission line. According to the transmission line theory, the inductance can be equivalent to a length of microstrip line. The formula: wL=Ztan (Bl), w is the angular frequency 2pi*f, L is the inductance value, Z is the characteristic impedance of the microstrip line, and Bl is the electrical length. According to the data sheet, the pin width of the tube is about 0.5mm. When designing a microstrip line, a value with a similar width should be selected to simulate that the impedance changes too much. Here, a microstrip line with a width of 0.5mm is selected.
Substituting the relevant values into wL=Ztan (Bl), the calculation shows that the Bl electric length is about 21.3 degrees, and the calculation is performed in LineCalc (see 06 for use of LineCalc, the distributed parameter matching of the ADS usage record), and here the microstrip line width is 23mm: follow the above steps to set the microstrip line parameters (FR4): replace the source inductance with an equivalent microstrip line: perform the simulation below, and find that the simulation results are basically the same: analyze the input and
output 
impedances
below
. When designing the low-noise amplifier this time, priority was given to noise performance, and the minimum noise matching was performed here. It was observed that the input and output impedances were as follows: 50 ohms were used as the characteristic impedance of the transmission line, and the input
and output impedances needed to be matched to 50 ohms.
7. Input and output impedance matching
Modify the above schematic diagram to make the schematic diagram look better: 
replace all devices with real devices: add
microstrip pads to all resistors, capacitors and chips, use joints to connect at the junction, and use FR4 boards for the board:
simulate and observe the input impedance at this time:
match the input below, insert the circle diagram matching control, and add it to the input side:
disconnect the microstrip connection at the back, and insert a new port. The port impedance is 105.2-j34, which is the conjugate of the above port impedance:
Double-click the smith chart control, and set the control parameters as follows (here set the load impedance 105.2+j34):
Find smithchart in Tool and open it, input source impedance and load impedance, click automatic 2 component matching, and select the matching method of series inductors and capacitors:
After the design is completed, check the matching effect (it seems to be very good at this time):
copy the resistor and capacitor to the main schematic diagram, and add the microstrip pad: 
pay attention to the length and width of the microstrip line:
对匹配的电感电容进行tuning，观察s11参数，发现在电感为20nH，电容为2pf时匹配最好，S11可达-38db：
将电感电容换为实际的电感电容，在此进行仿真：
在此仿真得到实际元件的S11，性能有所下降但可以接受（电容电感暂时还不能完全确定，需要等之后全部原理图一起仿真后确定）：
下面进行负载端匹配，之前负载端阻抗为：193+j92欧姆：
插入端口与smith控件如下所示（注意设置端口阻抗193-j92欧姆）：
对smith控件进行设置（注意设置此时的负载阻抗为193+j92，这与之前源阻抗匹配不一样，十分重要）：
设置完成后自动生成2元件匹配，查看匹配性能：
性能很好，下面添加微带线焊盘与连接并对电感电容进行调谐，发现使用实际电感33nH，电容1.5pf时S22参数较好：
8. Layout drawing and simulation
The final circuit diagram is as follows:
click the menu layout to update the circuit diagram: the
generated layout is as follows (the middle is the tube, because there is no package and the code is garbled): correct the layout,
delete all the inductance and capacitance components and ground wires and add ports:
click EM settings:
set the board material FR4, the board height is 20mil, the copper thickness is 35um and other related parameters: set the
frequency sweep parameters: set the
output strategy:
click simulation, and the simulation is completed after a period of time:
go back to EM settings, click the symbol button: click the
device generator at the bottom right:
click look like option, and set the zoom factor to 0.03: Click
OK to generate the schematic symbol (this is the microstrip line designed before):
9. Co-simulation
Create a new schematic, find the generated symbol in the library and insert it:
Connect the symbols, add inductors, capacitors, and power supplies, which are consistent with the previous schematic diagram: 
set the S parameter sweep to be consistent with the sweep strategy of the previous layout simulation, and enable the noise calculation function of the S simulation controller: the following co-simulation settings, select the
Choose View For Simulation button (on the left of the simulation button): click the layout
symbol just inserted, and select the emmodel option in the pop-up window;
Everything is ready to co-simulate this schematic. The final result graph is obtained. The S21 parameter is 18.5db, indicating that the gain of the LNA is about 18.5db. The S11 parameter is -26.5db. This parameter affects the standing wave. The performance of this S11 parameter is acceptable: observe the noise performance and find that the noise has deteriorated by about 0.2, which is already very ideal. Observe the stability. The stability coefficient is 1.137 greater than 1, and the system is absolutely stable and meets the requirements
.
In summary, a low noise amplifier with a gain of 18.5db and S11 of -26.5db is designed. The system noise performance is excellent, the center frequency is 433MHZ, and the symbol design requirements.
TIPS:
The impedance relationship of the input terminal during impedance matching:
The input impedance measured by the ADS control is Z1, and the port impedance added during matching is the conjugate of Z1. When setting the Smith matching control, ZL is set to be the conjugate of Z1 .
Output impedance relationship during impedance matching:
The output impedance measured by the ADS control is Z2, and the port impedance added during matching is the conjugate of Z2. When setting the Smith matching control, Zg is set to be the conjugate of Z2, that is, Z2 itself . The Smith matching control needs to additionally set the source type to input:
I don't know why this is the case (the conjugated part over there), but the result is correct.