Summarize the knowledge points of STM32 embedded interview

1. What is the difference between STM32F1 and F4?

Different cores: F1 is Cortex-M3 core, F4 is Cortex-M4 core; main frequency is different: F1 main frequency is 72MHz, F4 main frequency is 168MHz; The design is richer and more powerful than F1, such as GPIO flip rate, pull-up and pull-down resistor configuration, ADC precision, etc.; memory size: F1 internal SRAM maximum 64K, F4 has 192K (112+64+16).

2. Introduce the STM32 startup process

Through the Boot pin setting, look for the initial address to initialize the stack pointer __initial_sp points to the reset program Reset_Hander sets the exception interrupt HardFault_Handler sets the system clock SystemInit calls the C library function _main

3. Introduce GPIO

GPIO 8 working modes (gpio_init.GPIO_Mode):

(1) GPIO_Mode_AIN analog input

(2) GPIO_Mode_IN_FLOATING floating input

(3) GPIO_Mode_IPD pull-down input

(4) GPIO_Mode_IPU pull-up input

(5) GPIO_Mode_Out_OD open-drain output

(6) GPIO_Mode_Out_PP push-pull output

(7) GPIO_Mode_AF_OD multiplexed open-drain output

(8) GPIO_Mode_AF_PP Multiplexing push-pull output APB2 is responsible for AD, I/O, advanced TIM, serial port 1.

APB1 is responsible for DA, USB, SPI, I2C, CAN, serial port 2345, ordinary TIM, PWR

4. UART

• Question 1: Introduction to serial communication

Synchronous communication: I2C half duplex, SPI full duplex

Asynchronous communication: RS485 half duplex, RS232 full duplex

• Question 2: Serial port configuration

The general steps of serial port setting can be summarized as the following steps:

(1) Serial port clock enable, GPIO clock enable (2) Serial port reset (3) GPIO port mode Set the GPIO working mode of TX to: GPIO_Mode_AF_PP; //The GPIO working mode of multiplexed push-pull output RX is: GPIO_Mode_IN_FLOATING; / /float input

(4) Serial port parameter initialization mainly includes: baud rate setting (115200), 8 data bits, 1 stop bit, no parity bit, no hardware data flow control, and transceiver mode. (5) Turn on the interrupt and initialize the NVIC (this step is only required if you need to turn on the interrupt)

(6) Enable the serial port

(7) Write interrupt processing function

• Question 3: Main features of USART

(1) Full-duplex operation (receiving data and sending data independently of each other);

(2) During synchronous operation, the master clock can be synchronized, and the slave clock can also be synchronized;

(3) Independent high-precision baud rate generator, which does not occupy the timer/counter;

(4) Support serial data frame structure of 5, 6, 7, 8 and 9 data bits, 1 or 2 stop bits;

(5) Parity generation and inspection supported by hardware;

(6) Data overflow detection;

(7) Frame error detection;

(8) Detection noise filter and digital low-pass filter including false start bits

(9) Three completely independent interrupts, TX transmission completed, TX transmission data register empty, RX reception completed;

(10) Support multi-machine communication mode;

(11) Support double-speed asynchronous communication mode.

Application scenarios: GPS, Bluetooth, 4G modules

5. I2C

Question 1: There are three types of signals in the I2C bus in the process of transmitting data

(1) Start signal: When SCL is high level, SDA jumps from high level to low level, and starts to transmit data.

(2) End signal: When SCL is high level, SDA jumps from low level to high level, and the data transmission ends.

(3) Response signal: After receiving the 8bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After receiving the response signal, the CPU makes a judgment on whether to continue to transmit the signal according to the actual situation. If no response signal is received, it is judged that the controlled unit is faulty.

Question 2: How to configure the hardware mode of the I2C host mode port: multiplex open-drain output, neither pull-up nor pull-down.

(Fast mode: 400 Kbit/s) Software simulation: push-pull output, configure pull-up resistor.

Question 3: I2C arbitration mechanism? I2C arbitration mechanism, understand the line "and" (Wired-AND), it is clear at a glance. Simply put, it follows the principle of "low level priority", that is, whoever sends low level first will take control of the bus.

Hardware mode: is set by the communication rate

/* STM32 I2C 快速模式 */
#define I2C_Speed 400000

/* 通信速率 */
I2C_InitStructure.I2C_ClockSpeed = I2C_Speed;

Software simulation: How to calculate the communication rate without setting it?

Through the I2C bus bit delay function i2c_Delay:

static void i2c_Delay(void)
{
  uint8_t i;

  /*
     下面的时间是通过安富莱AX-Pro逻辑分析仪测试得到的。
    CPU主频72MHz时，在内部Flash运行, MDK工程不优化
    循环次数为10时，SCL频率 = 205KHz
    循环次数为7时，SCL频率 = 347KHz， SCL高电平时间1.5us，SCL低电平时间2.87us
     循环次数为5时，SCL频率 = 421KHz， SCL高电平时间1.25us，SCL低电平时间2.375us

    IAR工程编译效率高，不能设置为7
  */
  for (i = 0; i < 10; i++);
}

Application scenarios: PMIC, accelerometer, gyroscope

Six, SPI

• Question 1: How many wires does SPI need?

The SPI interface generally uses 4 wires for communication: MISO master device data input, slave device data output. MOSI Master device data output, slave device data input. SCLK clock signal, generated by the master device. CS Slave device chip select signal, controlled by the master device.

• Question 2: Four modes of SPI communication?

SPI has four working modes. The difference between each working mode is that SCLK is different, and the specific work is determined by CPOL and CPHA.

(1) CPOL: (Clock Polarity), clock polarity. The CPOL of SPI indicates whether the level value of SCLK is low level 0 or high level 1 when SCLK is idle.

CPOL=0, the level when the clock is idle is low level, so when SCLK is valid, it is high level, which is the so-called active-high;

CPOL=1, the level when the clock is idle is high level, so when SCLK is valid, it is low level, which is the so-called active-low;

(2) CPHA: (Clock Phase), clock phase.

The phase corresponds to which edge (edge) the data sampling is on, whether it is the first edge or the second edge, 0 corresponds to the first edge, and 1 corresponds to the second edge.

CPHA=0, means the first edge:

For CPOL=0, when idle is low level, the first edge is from low to high, so it is a rising edge;

For CPOL=1, when idle is high level, the first edge is from high to low, so it is a falling edge;

CPHA=1, indicating the second edge:

For CPOL=0, when idle is low level, the second edge is from high to low, so it is a falling edge; for CPOL=1, when idle is high level, the first edge is from low to low to high, so it is a rising edge;

• Question 3: How to determine which mode to use?

(1) First confirm the SCLK polarity required by the slave, whether it is at low potential or high potential when it is not working, and thus confirm that CPOL is 0 or 1. Looking at the schematic diagram, we set the idle state of the serial synchronous clock to be high, so we choose SPI_CPOL_High. That is, CPOL is 1.

(2) From the timing diagram in the slave chip datasheet, confirm whether the slave chip collects data on the falling edge of SCLK or on the rising edge of SCLK.

Translate: W25Q32JV is accessed through an SPI compatible bus, including four signals: serial clock (CLK), chip select (/CS), serial data input (DI) and serial data output (DO).

Standard SPI instructions use the DI input pin to serially write instructions, addresses, or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation in modes 0 (0,0) and 3 (1,1) is supported.

Mode 0 and mode 3 focus on the normal state of the CLK signal when the master end of the SPI bus is in the standby state and the data is not transmitted to the serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.

Since the idle state of the serial synchronous clock is high, here we choose the second transition edge, so choose SPI_CPHA_2Edge. That is, CPHA is 1.

That is, we choose mode 3(1,1).

Application scenario: SPI Flash, W25Q32 memory capacity 32Mb (4M x 8), namely 4M byte

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7. CAN

• Question 1: CAN Summary Introduce the CAN controller to judge the bus level according to the potential difference between CAN_L and CAN_H. The bus level is divided into dominant level and recessive level, and the ratio of the two is one of them. The sender sends a message to the receiver by changing the bus level. Question 2: CAN initialization configuration steps? (1) Configure the multiplexing function of the relevant pins, enable the CAN clock (2) Set the CAN working mode and baud rate, etc. (CAN initialization loopback mode, baud rate 500Kbps) (3 ) Set the filter Question 3: CAN send data format

CanTxMsg TxMessage;TxMessage.StdId=0x12; //标准标识符
TxMessage.ExtId=0x12; // 设置扩展标示符
TxMessage.IDE=CAN_Id_Standard; // 标准帧
TxMessage.RTR=CAN_RTR_Data; // 数据帧
TxMessage.DLC=len; // 要发送的数据长度 发送8个字节
for(i=0;i<len;i++)
  TxMessage.Data[i]=msg[i]; //数据

8. DMA

• Question 1: DMA introduction?

Direct memory access (DMA) is used to provide high-speed data transfers between peripherals and memory, or between memory and memory. Data can be moved quickly through DMA without CPU intervention, which frees up CPU resources for other operations.

• Question 2: How many DMA transfer modes are there?

DMA_Mode_Circular circular mode DMA_Mode_Normal normal cache mode

Application scenarios: GPS, Bluetooth, both use circular acquisition, DMA_Mode_Circular mode.

A more important function is to obtain the current remaining data size, and subtract the current remaining data size from the set receiving buff size to obtain the current receiving data size.

Nine, interruption

• Question 1: Describe the interrupt processing flow? (1) Initialize the interrupt, set the trigger mode as rising edge/falling edge/double edge trigger. (2) Trigger an interrupt and enter the interrupt service function

• Question 2: How many external interrupts does the STM32 interrupt controller support?

The interrupt controller of STM32 supports 19 external interrupt/event requests:

From the figure, GPIO pins GPIOx.0~GPIOx.15 (x=A, B, C, D, E, F, G) correspond to interrupt lines 0 ~ 15 respectively.

The other four EXTI lines are connected as follows: ● EXTI line 16 is connected to the PVD output ● EXTI line 17 is connected to the RTC alarm event ● EXTI line 18 is connected to the USB wakeup event ● EXTI line 19 is connected to the Ethernet wakeup event (only for Interconnected products) Interrupt service function list: IO port external interrupts are only assigned 7 interrupt vectors in the interrupt vector table, that is, only 7 interrupt service functions can be used. EXTI0_IRQHandlerEXTI1_IRQHandlerEXTI2_IRQHandlerEXTI3_IRQHandlerEXTI4_IRQHandlerEXTI9_5_IRQHandler

EXTI15_10_IRQHandler

Ten, STM32 has several clock sources

STM32 has 5 clock sources: HSI, HSE, LSI, LSE, PLL.

①, HSI is a high-speed internal clock, RC oscillator, the frequency is 8MHz, the precision is not high.

②, HSE is a high-speed external clock, which can be connected to a quartz/ceramic resonator, or an external clock source, and the frequency range is 4MHz~16MHz.

③. LSI is a low-speed internal clock, an RC oscillator with a frequency of 40kHz, which provides a low-power clock.

④, LSE is a low-speed external clock, connected to a quartz crystal with a frequency of 32.768kHz.

⑤. PLL is a phase-locked loop multiplier output, and its clock input source can be selected as HSI/2, HSE or HSE/2. The frequency multiplier can be selected as 2~16 times, but the maximum output frequency should not exceed 72MHz.

11. How is the task of RTOS written? How to cut out this task?

answer:

A task is also called a thread. UCOS has a task scheduling mechanism, which is scheduled according to the priority of tasks. One is a hardware interrupt, then the system will push the relevant variables of the current task into the stack, then execute the interrupt service routine, and return after the execution is completed. The other is the switching between tasks. The method used is task scheduling, and each task has its own The stack, the scheduling is also pushed into the stack, and then another program is executed, and then popped and returned.

Not every task is executed in turn according to the order of priority, but high priority tasks run exclusively, unless they voluntarily give up execution, otherwise low priority tasks cannot be preempted, and high priority tasks can be released to low priority tasks Use the right to grab back the CPU usage. Therefore, attention should be paid to inserting a waiting delay between ucos tasks so that ucos can be switched out to allow low-priority tasks to execute.

12. What are the communication methods between tasks in UCOSII?

answer:

In UCOSII, semaphores, mailboxes (message mailboxes) and message queues, which are called events, are used to implement communication between tasks, as well as global variables. The semaphore is used to: 1. Control the right to use shared resources (satisfy mutual exclusion conditions)

2. Mark the occurrence of a certain time

3. Synchronize the behavior of 2 tasks

Application example: mutual exclusion semaphore

As a mutual exclusion condition, the semaphore is initialized to 1.

To achieve the goal: to call the serial port to send a command, you must wait for the "OK" character to be returned before sending the next command. Each task may use this send function, no conflicts can occur!

message queue:

concept:

(1) The message queue is actually a mailbox array

(2) Both the task and the interrupt can put a message into the queue, and the task can get the message from the message queue.

(3) The message that enters the queue first is passed to the task (FIFO).

(4) Each message queue has a waiting list of tasks waiting for messages. If there is no message in the message column, the tasks waiting for messages will be suspended until the message arrives.

Application scenario: the receiving buffer in the serial port receiving program.

Store external events.

13. The project uses a custom protocol, what is the structure?

answer:

The structure is: frame header (SDTC) + frame length + command + serial number + data + CRC check.

14. What is the difference between uCOSII and Linux?

answer:

μC/OS-II is specially designed for computer embedded applications. μC/OS-II has the characteristics of high execution efficiency, small footprint, excellent real-time performance and strong scalability. The minimum kernel can be compiled to 2KB. μC/OS-II has been ported to almost all well-known CPUs.

Linux is free, safe, stable, and has a wide range of applications. It is widely used in embedded systems, servers, and home computers.

μC/OS-II Linux are suitable for use in embedded. But μC/OS-II is specially designed for embedded, so the result is that it runs more efficiently and takes up less resources.

Linux can be used as a server, and the usage rate is high. Although linux is not developed specifically for servers, its source code is open and can be modified completely, so that the difference between the two is not big. The most important distribution version, redhat linux, is a system that is used a lot on servers.

15. Git commit code

Question: Git commit code process?

answer:

1. Display the modified files in the working path:

$ git status

2. Enter the modification file directory:

$cd -

3. Display the difference from the last submitted version file:

$ git diff

4. Add all current changes to the next submission:

$ git add .

5. Add relevant function descriptions, (use this for the first submission)

$ git commit -s

It should also be noted:

Fuction: The function of modifying the code Ticket: Corresponding to the Bug number

Note: Each folder must be mentioned again.

6. View the submitted code

$ tig .

7. Do not modify the published submission record! (Use this for future submissions)

$git commit --amend

In command mode:

:x (write to file and exit)

8. Push to the server

$ git push origin HEAD:refs/for/master

Sixteen, comparison between ucosii and ucosiii and freeRTOS

• Question 1: How do the three compare?

answer:

Comparison between ucosii and freeRTOS:

(1) freeRTOS only supports TCP/IP, while uCOSii has a lot of extension support, such as FS, USB, GUI, CAN, etc. (We use CAN for tbox, so we choose uCOSii) (2) freeRTOS is a free commercial application. Commercial use of uCOSii is subject to payment. (3) Inter-task communication freeRTOS only supports queues, semaphores, and mutexes. In addition to these, uCOSii also supports event flag groups and mailboxes.

(4) Theoretically speaking, freeRTOS can manage more than 64 tasks, while uCOSii can only manage 64 tasks.

Comparison between ucosii and ucosiii:

So what are the differences from μC/OS-II to μC/OS-III? What has been added, we see that the changes are still very large.

One is that there were only 0~63 priorities in the past, and the priorities cannot be repeated. Now several tasks are allowed to use the same priority, and in the same priority, the time slice scheduling method is supported;

The second is to allow users to dynamically configure real-time operating system kernel resources during program execution, such as tasks, task stacks, semaphores, event flag groups, message queues, message numbers, mutex semaphores, memory block division, and timers , which can be changed while the program is running. In this way, users can avoid the problem of insufficient resource allocation during program compilation.

In terms of resource reuse, some improvements have also been made. In μC/OS-II, the maximum number of tasks is 64, and after version 2.82, it is 256. In μC/OS-III, users can have any number of tasks, any number of semaphores, mutual exclusion Flags, message lists, timers, and arbitrarily allocated memory block sizes are limited only by the amount of RAM available to the user's CPU. This one is also a big extension.

(Question: Mr. Shao, is this number fixed at startup, or is it set randomly after startup?) It can be freely defined during configuration, as long as your RAM is large enough.

The fourth point is that many functions have been added. There are always more and more functions. You can take a look at them. It turns out that these functions are not available in μC/OS-II.

Seventeen, low power consumption mode

• Question 1: How many low-power modes are there? What is the wake-up method?

answer:

18. Architecture of the Internet of Things

• Question 1: How many layers is the architecture of the Internet of Things? What functions are each layer responsible for?

answer:

Divided into three layers, the Internet of Things can be divided into perception layer, network layer and application layer from the architecture

(1) Perception layer: Responsible for information collection and information transmission between objects. Information collection technologies include sensors, barcodes and two-dimensional codes, RFID radio frequency technology, audio and video and other multimedia information.

Information transmission includes sensor networks such as long-distance data transmission technology, self-organizing networking technology, collaborative information processing technology, and information collection middleware technology.

The perception layer is the core capability to realize the comprehensive perception of the Internet of Things. It is a part of the Internet of Things that needs breakthroughs in key technologies, standardization, and industrialization. issues of cost and cost.

(2) Network layer: It uses wireless and wired networks to encode, authenticate and transmit the collected data. The widely covered mobile communication network is the infrastructure for realizing the Internet of Things. It is the most standardized and industrialized network among the three layers of the Internet of Things. The key to the most capable and mature part is to optimize and improve the application characteristics of the Internet of Things to form a collaborative sensing network.

(3) Application layer: To provide rich applications based on the Internet of Things is the fundamental goal of the development of the Internet of Things. Combining the Internet of Things technology with the needs of industry informatization to achieve a wide range of intelligent application solution sets, the key lies in industry integration, Development and utilization of information resources, low-cost and high-quality solutions, guarantee of information security and development of effective business models.

Nineteen, memory management

• Question 1: What are the methods of memory management in UCOS?

answer:

The system manages the memory partition through the memory control block associated with the memory partition.

The dynamic memory management functions are:

Create dynamic memory partition function OSMemCreate(); request memory block function OSMemGet();

Release memory block function OSMemPut();

20. What are the task states in Ucos? A graph of the relationship between task states?

answer:

There are 5 states:

Sleep state, ready state, running state, wait state (waiting for an event to occur) and interrupt service state.

5 state transition relationships of UCOSII tasks:

21. ADC

Briefly describe the functional characteristics of STM32's ADC system (1) 12bit resolution (2) automatic calibration (3) programmable data alignment (conversion results support left-aligned or right-aligned storage in 16-bit data registers) (4) single and Continuous Conversion Mode

22. System Clock

• Briefly describe the basic process of setting the system clock

(1) Turn on HSE, wait for ready, set Flash to wait for operation. (2) Set the frequency division coefficients of AHB, APB1, and APB2 to determine the relationship between them and the system clock. (3) Set the CFGR register to determine the clock source and multiplication factor of the PLL (HSE external 8M*9 times=72MHz).

(4) Enable the PLL and switch the system clock source to the PLL.

Twenty-three, HardFault_Handler processing

• Question 1: Causes

(1) Array out-of-bounds operation; (2) Memory overflow, access out-of-bounds; (3) Stack overflow, program runaway; (4) Interrupt processing error;

• Question 2: How to deal with it

(1) Find the address remapping of HardFault_Handler in startup_stm32f10x_cl.s, and rewrite it so that it jumps to the HardFaultHandle function.

(2) Print and check R0, R1, R2, R3, R12, LR, PC, PSR registers.

(3) View the Fault status register group (SCB->CFSR and SCB->HFSR)

24. TTS Speech Synthesis Method

• Question 1: What method does sim7600 TTS voice use

answer:

(1) Synthesize sound using unicode encoding

AT+CTTS=1,” 6B228FCE4F7F75288BED97F3540862107CFB7EDF”

The content is "Welcome to the Speech Synthesis System". The module sends and receives Chinese text messages with unicode encoding, so it is easy to read the text messages;

(2) Input text directly, common characters adopt ASIIC code, and Chinese characters adopt GBK code.

AT+CTTS=2,"Welcome to the Speech Synthesis System"

25. Timer

• It is known that the system clock of STM32 is 72MHz, how to set the relevant registers to achieve 20ms timing?

answer:

Via SysTick_Config(SystemCoreClock / OS_TICKS_PER_SEC))//1ms timer

in:

uint32_t SystemCoreClock  = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */ #define SYSCLK_FREQ_72MHz  72000000 #define OS_TICKS_PER_SEC       1000    /* Set the number of ticks in one second

If you need 20ms, you can set a global variable and set the initial value to 20. In this way, each systick is interrupted once, and the global variable is reduced by 1 and reduced to 0, that is, the systick is interrupted 20 times, and the time is: 1ms*20 =20ms. Thus a timing of 20ms is achieved.

Twenty-six, state machine

• Question: What state machine is used?

answer:

(English: Finite-state machine, FSM), also known as finite state automaton, referred to as state machine.

Suppose the state transition of the state machine is shown in the following table:

Implementation: (using switch statement)

//横着写
void event0func(void)
{
    switch(cur_state)
    {
        case State0:
             action0;
             cur_state = State1;
            break;
         case State1:
             action1;
             cur_state = State2;
            break;
         case State2:
             action1;
             cur_state = State0;
            break;
        default:break;
    }
}

void event1func(void)
{
    switch(cur_state)
    {
        case State0:
             action4;
             cur_state = State1;
             break;
        default:break;
    }
}

void event2func(void)
{
    switch(cur_state)
    {
        case State0:
             action5;
             cur_state = State2;
            break;
         case State1:
             action6;
             cur_state = State0;
            break;
        default:break;
    }
}

Twenty-seven, device selection

STM32F407 VS STM32F103 main function and resource comparison?

answer: