[Summary] Embedded interview related knowledge points

Interrupt tail docking

When multiple interrupts are triggered at the same time, the high-priority interrupt interrupt response does not need to be restored to the operating environment, but the next-highest priority interrupt is directly executed, and the operating environment is restored after all interrupts are executed. With interrupt tail docking function, you can save two stack operations.

SWD debug interface

SWD only needs to use the two pins of the chip (SWDIO SWCLK) to realize the online simulation and debugging of the core chip. Using SWD can fix the program to the chip flash memory, and has the function of instruction tracking execution.
There are several advantages:

1. SWD is more reliable in high-speed mode. In the case of a large amount of data, the JTAG download program may fail, but the probability of SWD occurrence will be much smaller. Basically, the SWD mode can be used directly when the JTAG emulation mode is used.
2. When one GPIO port is missing, we can use SWD emulation, which supports fewer pins.
3. When planning and designing the board, it is recommended to use the SWD mode, which requires fewer pins and requires less PCB space.

JTAG debug interface

JTAG (Joint Test Action Group, Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compatible), mainly used for internal chip testing. Now most advanced devices support JTAG protocol, such as ARM, DSP, FPGA devices and so on. The standard JTAG interface is 4 wires: TMS, TCK, TDI, TDO, which are the mode selection, clock, data input and data output lines respectively. The definition of the relevant JTAG pins is:

• TMS: Test mode selection, TMS is used to set the JTAG interface in a specific test mode;
• TCK: Test clock input;
• TDI: Test data input, the data is input to the JTAG interface through the TDI pin;
• TDO: Test data output, data is output from the JTAG interface through the TDO pin;

Harvard structure and von Neumann structure

The Harvard structure is used for high-speed data processing because instructions and data (stored separately) can be read at the same time. Greatly improve the data throughput rate, the disadvantage is that the structure is complex. General-purpose microcomputer instructions and data are mixed storage, simple in structure and low in cost. Suppose it is a Harvard structure: you have to install two hard disks in your computer, one for programs, one for data, and two for memory, one for instructions and one for data... The
structure depends on the bus structure. Although the data instruction storage area of ​​51 single-chip microcomputer is separated, the bus is time-division multiplexed, so at most it can be regarded as an improved Harvard structure. Although ARM7 ARM9 is a Harvard structure , the previous version is also a von Neumann structure. The early X86 can quickly occupy the market, a very important reason is precisely relying on von Neumann's simple and low-cost bus structure. Although the processor appears to have a Neumann structure on the external bus, due to the existence of the internal CACHE, it is actually an improved Harvard structure internally.

Von Neumann structure: arithmetic unit, controller, memory, input device, output device

RAM write back mode (write back)

The area with RAM write-back mode is also called fast RAM area. When the kernel writes data to RAM, it does not directly write data to RAM, but writes it to a faster cache. When the cache is full or the bus is free , The data in the cache is automatically written to the RAM area. Therefore, the data in the RAM of the write-back feature may be different from the data in the cache. When the data is small, the data will be stored in the cache instead of being written to the RAM.

On-chip RAM (SRAM) is generally a cache mechanism with write-back characteristics

RAM write through mode (write through)

When the kernel writes data to the RAM area, it directly writes the data to the ram area through the cache. Under the write-through feature, the data in the RAM and the data in the cache are the same.

Word address half word address

Word address: the lowest two bits of the address are 0, such as 0x0000 0000, 0x0000 0004, 0x0000 0008;
half-word address: the lowest bit of the address is 0, such as 0x0000 0000, 0x0000 0002, 0x0000 0004; the
word addresses are all half-word addresses

Big-endian modeLittle-endian mode

In little endian mode: the high byte of the data word is stored at the high end of the word address, and the low byte of the data word is stored at the low end of the word address;
big endian mode: the high byte of the data word is stored at the low end of the word address, The low byte of the data word is stored at the high end of the word address; the
big-endian mode is order-preserving, and the order of the bits in each byte remains unchanged from high to low. The
server is generally big-endian

Process mode and handle mode

ARM instruction set and Thumb instruction set

Because Thumb instruction may be more effective than ARM instruction in some special cases, it has been widely used in many aspects. However, Thumb is a subset of the ARM instruction set, which cannot independently form an application system. Therefore, in many cases, applications require mixed programming of the two, which will inevitably have the problem of function calls between ARM and Thumb states.

The state switch between ARM/Thumb is realized through a special transfer exchange instruction BX. The BX instruction uses general-purpose register bit operands to realize an absolute jump within the 4GB space by copying Rn to the PC. BX uses the last bit of the destination address value in the Rn register to determine the state after the jump. When the last bit is 0, it means transition to ARM state; when the last bit is 1, it means transition to Thumb state.