ch6_3 Operation method in computer

1. Fixed-point arithmetic

1.1 Shift operation

Note that there are two ways of shifting here,
one is to shift the decimal point to the right,

Another one, the decimal point does not move, and the numerical part moves relative to the decimal point,

1.1.1 The meaning of displacement

When left shift and right shift refer to moving the numerical part,
at this time, the absolute value of left shift expands; right shift, the absolute value shrinks.

而在计算机中，一般左移右移指的便是，小数点不动，移动数值部分。
从而，移位与加减配合，能够实现乘除运算

1.1.2 Arithmetic Shift Rules

• For positive numbers, the sign bit of the three machine numbers remains unchanged after shifting. When shifting to the left, the highest digit is lost by 1, resulting in an error. When shifting to the right, the lowest digit is lost by 1, which affects the accuracy.

• When the original code of a negative number is shifted to the left, the high bit is lost by 1, and the result is wrong. When it is shifted to the right, the low bit is lost by 1, which affects the accuracy.

• When the complement of a negative number is shifted to the left, the high bit is dropped as 0, and the result is an error; when it is shifted to the right, the low bit is dropped as 1, which affects the accuracy.

1.1.3 Hardware implementation of arithmetic shift

The upper line represents the case of left shift;

The next line represents the case of right shift;

1.1.4 Difference between arithmetic shift and logical shift

The difference between arithmetic and logic lies in whether the highest bit is a sign bit;

• The shift of signed numbers is called arithmetic shift, and the shift of unsigned numbers is called logical shift.

• During the arithmetic shift process, the sign bit does not participate in the shift;

1.2 Addition and subtraction

The only machine numbers that are true-valued 0 representations are, complement and shift;

The implementation idea of ​​subtraction: 找到一个与负数等价的正数，　来代替这个负数, thus using addition to complete subtraction in the actual sense;

1.2.1 Complement code addition and subtraction formula

Added together with the sign bit, the carry generated by the sign bit is naturally discarded;

The problem caused by this, the sign bit will cause the overflow problem;

1.2.2 Overflow Judgment

One-bit sign bit judges overflow:
the two numbers participating in the operation have the same sign, and
the sign of the result is different from the sign of the original operand,
which means overflow ; .

Hardware implementation:
Carry of the most significant bit XOR sign bit = 1, overflow;

Two sign bits judge overflow;

Hardware configuration for complement addition and subtraction;

1.3 Multiplication

乘法运算，可以通过加法和移位运算来是实现

The number of additions is the same as the number of shifts.　
The last bit of the multiplier determines whether the multiplicand is added to the original partial product.
Then, -> 1 bit forms a new partial product. At the same time, the multiplier -> 1 bit, the last bit is discarded , to free up the low bit of the high bit storage partial product.
The multiplicand is only added to the high order bits of the partial product

Hardware, 3 registers, two of which have shift functions,
　1 full adder

• The last bit of the multiplier determines whether the multiplicand is added to the original partial product,

• Then shift right by 1 bit to form a new partial product. At the same time, the multiplier is shifted to the right by 1 bit, and the last bit is lost, leaving the high bit to store the low bit of the partial product.

• The multiplicand is only added to the high order bits of the partial product

• Hardware required: 3 registers, two of which have shift functions,

• a full adder.

• Original code multiplication
  

• Two's complement multiplication
  

The process of integer multiplication is exactly the same as that of decimal multiplication, and the decimal point can be replaced by a comma;
the original code multiplication, the sign bit is processed separately;
the complement code multiplication, the sign bit is formed naturally;

The original code multiplication removes the sign bit operation, which is the multiplication of unsigned numbers;
different multiplication operations require different hardware support.

The multiplicand is placed in the X register,
the multiplier is placed in the multiplication quotient register, and the high bit of the accumulated value of the multiplication is placed in the acc register. The value of the acc register becomes longer during the right shift, and the lowest bit is moved to the MQ register. , the multiplier stored in the mq register is also shifted to the right, and every time it is shifted to the right, the lowest bit that has been used will be discarded.

Understand the train of thought, analyze the process of multiplication with written calculations, improve the multiplication with written calculations, and perform multiplication with original code.

In the multiplication of one bit in the original code, the number of shifts is used to judge whether the multiplication is over.

1.4 Division operation

The determination of the division quotient of the pen calculation can be realized as long as an exclusive OR circuit is used.

A 2-times word-length adder is required in pen-based division, while only a 1-times word-length adder is required in machine division.

• original code division

Convention:　
In original code division, it is agreed that the absolute value of the dividend in decimal fixed-point division should be smaller than the absolute value of the divisor.

• restore remainder division
  

If the remainder is positive, the upper quotient is 1; if
the remainder is negative, the upper quotient is 0, and the remainder is restored;

• Non-recovery remainder method (addition and subtraction alternate method)

2. Four arithmetic operations of floating point

In computers, addition and subtraction use complement code;
because of the characteristics of complement code, subtraction can be converted into addition;

2.1 Definition of order

Why match up?
Because, in the process of order, it is guaranteed that the order codes of the two floating-point numbers are the same, and at this time, the mantissa in the floating-point number needs to be adjusted accordingly.
The adjusted digits can be directly added and subtracted.

The order-alignment principle of floating-point addition and subtraction operations is that the small order is aligned with the large order;
the reason for this is:

If the large order is aligned with the small order, the order of the large order needs to be shifted to the right,
and the highest order of the order will be discarded during the process of shifting to the right. Due to the discarded highest order data, the value of the order itself will be directly changed The size of the value is no longer the original number involved in the operation, resulting in an error;

Correspondingly, if the small order is aligned with the large order, the number of the small order is shifted to the left. During the moving process, the lowest digit is discarded, which affects the data accuracy. Such an operation result is acceptable;

2.2 The process of step code matching

The order code and the mantissa character in the exponent code and the mantissa are represented by two digits.
In the process of finding the complement code,　
the order sign and the end sign remain unchanged, and
only the order and mantissa part are represented by complement code.

• Complement code representation
  Here, the value before the semicolon represents the value of the exponent code, represented by four digits, of which the exponent occupies two digits;
  after the semicolon represents the mantissa part, represented by six digits, and the exponent occupies two digits;

• Find the step difference
  

在求阶差过程中，注意：　　$-[j_y]Complement$　In the process of converting into an addition operation, it is necessary to invert the order part of the order code; while the order part is a complement operation;

• Opposite order
  

2.3 Normalization in floating-point numbers

Why normalize the mantissa of a floating point number?

The leading zeros in the value will occupy more digits, and the normalized mantissa will reduce the number of digits occupied by zeros;

For example, 3/4 is 0.11, the significant figure is 11 with 2 digits, but 3 digits are used for the number 0.11; and 3/16, 0.0011, the significant figure is still only 2 digits, but the number has increased to 5 digits. What to do at this time, write $1.1\ast 2^{-1}$ , and$1.1\ast 2^{-3}$ , the leading zeros are eliminated.

At the same time, we found that, except for 0, the first digit of a valid number must be 1, so this 1 can also be omitted, so the above two numbers become .1e-1 and .1e-3, and only 1 digit is used to represent 2 significant figures.
This representation, which omits the leading 1, is the "normalization" specified by IEEE 754, which reduces the number of required significant digits by one, or increases the number of allowed significant digits by one. .

That is, the purpose of using normalized floating-point numbers is to increase the representation precision of data.

No matter the original code is positive or negative, the first digit is 1’s
complement sign bit and the first digit is different

当使用是补码方式表示机器数时:
左规:
In order to ensure that the value after left-handing remains unchanged, after the mantissa is left-shifted, it is necessary to subtract one from the order of the number at the same time.

右规:
After the mantissa is shifted to the right, the mantissa becomes smaller. In order to ensure that the overall value remains unchanged after the right shift, it is necessary to add one to the order part in the exponent;

practise:

2.4 Rounding

In the process of order alignment and right-hand rule, there may be
errors caused by the loss of the last digit of the mantissa, and rounding needs to be considered
(1) 0 rounding 1 rounding method
(2) constant "1" method

这里，注意到，在对阶过程，阶码部分进行加减一之后，在对尾数，左移还是右移的过程中，需要包含符号位，一起进行左移或者是右移

2.5 Overflow

Assuming that the machine number is a complement code and the mantissa is a normalized form, and assuming that the
exponent takes 2 bits, the value part of the exponent code takes 7 bits, the number sign takes
2 bits, and the mantissa takes n bits, then the complement code on the number axis Expressed as:

3. Arithmetic logic unit

3.1 ALU circuit

The combinational logic circuit has no memory function, so in order to save the output result, additional registers need to be added.

3.2 Serial carry chain

Carry Chain Transmission Carry Circuit Serial
Carry Chain Carry Serial Transmission

Taking the 4-bit full adder as an example, the carry expression of each bit is:

3.3 Parallel carry chain (carry ahead, carry skip)

The carry of the n-bit adder is generated at the same time. Take the 4-bit adder as an example:

• Single group skip carry chain
  n-bit full adder is divided into several groups, the carry in the group is generated at the same time, and the
  serial carry is adopted between the groups.

The single group skip carry chain is to divide the n-bit full adder into several groups, the carries in the groups are generated simultaneously, and the groups are carried out serially.

• double packet skip carry chain

The n-bit full adder is divided into several large groups, and the large groups contain several small groups.
The highest carry of the small group in each large group is generated at the same time.
Serial carry is adopted between large groups.