First, the basic binary adder / subtracter
Half adder
without considering the carry bit
without considering the carry bit
Various logic gates graphical symbols
1. a full adder
Commonly used full adder logic circuit
2.n-bit ripple-carry adder-
n 1-bit full adder (FA) can be cascaded in a n-bit ripple-carry adder-subtracter.
Line (xing) waves carry: Serial carry, high computing to wait for low carry reached to perform, and different from the position or travel-ahead.
Interpretation of the ripple carry adder / subtracter
1. The ripple carry add / subtractor
n 1-bit full adder (FA) can be cascaded in a n-bit ripple-carry adder-
2.M input line is controlled (for controlling the addition or subtraction):
When M = 0, for the addition (A + B) operation;
When M = 1, subtract (A- B) operation;
Specific areas,
[AB] Complement = [A] Complement + [- B] Complement
Known [B] up by M = 1, to give [-B] Complement
3. The overflow detection logic circuit using a single symbol bit Method:
When Cn = Cn-1, without overflow;
When Cn ≠ Cn- 1, the arithmetic overflow, J overflow signal is generated by the exclusive OR gate.
Delay time 4.n bit ripple carry adder of the ta calculated
Current bit full and Si must be such as to lower the carry Ci-1 came, and the number of digits for addition time.
Definition of T: single-stage logic circuit unit gate delay, T usually a "NAND" gate or a "NOR" gate delay time as a unit of measure.
3T: XOR gate delay time
After opening the adder after 3T: determining the operation is an addition or subtraction operation
For a full adder (FA) for, Si 6T delay time (delay per stage XOR gate 3T); Ci + 1 is the time delay of 5T.
After the summer open through 6T: Each full adder Ai⊕Bi deserves to
After opening the adder through 8T: C0 obtained by the value of C1
After completion of the last carry-consuming 3T: overflow detection completion
During the entire carry-propagation simultaneously obtained in each Si
Delay time ta n-bit ripple carry adder is: ta = 3T + 3T + n: 2T + 3T = n.2T + 9T = (2n + 9) T
When seen from the above equation, using the ripple carry adder, the more bits, the longer the delay time. And the like may also be employed a method to reduce lookahead calculation time.
Ta of the input addend input of the adder and the addend, in the worst case the output of the adder to obtain the most stable time required summation output.
ta small as possible.
The ripple carry adder composed of the disadvantages of a full adder (FA):
Disadvantages:
(1) into a serial bit length of its calculation time;
(2) only two operations to complete the addition and subtraction logic operations can not be completed.
Multifunctional arithmetic / logic unit (ALU):
Not only has the functions of arithmetic and logic operations;
But also ahead carry logic.
Thereby achieving high-speed operation.
Second, the fixed-point multiplication
1. Hand multiplication algorithm
Let n-bit multiplicand and the multiplier is represented by a decimal point
Multiplicand [x] Original = xf. Xn-1 ... x1x0
Multiplier [y] Original = yf. Yn-1 ... y1y0
The product
[Z] = 原 (xf⊕yf) + (0. Xn-1 ... x1x0) (0. In-1 ... y1y0)
Where, xf is the multiplicand sign, yf is the multiplier symbol.
Operation rule (1) the product of the symbols: n is multiplied with the number, multiplied by a negative number iso.
(2) Manual Operation:
Setting x = 0.1101, y = 0.1011
People used machines and difference algorithms at:
(1) machines typically only n bits long, the multiplication of two n bits, may be 2n-bit product.
(2) two operands could not do an adder for adding a product of an n-bit arithmetic add up.
2. Suitable forms of fixed-point machines
In order to fit two operands adder for adding the x · y rewritten in the form below:
According to this formula, parentheses may be expressed at different levels in the formula, sequentially shifting outwardly from accumulating inside.
an n-bit fixed-point general, provided the multiplicand x, y multiplier is less than 1, positive:
x=0.x1x2......xn <1
y = 0.y1y2 ...... is <1
Forming a recurrence formula
3. a flow chart multiplication original code
High base multiplication:
Multiplication discussed above are only examined by a bit. Also check whether the K-bit binary bits? To K = 2, C = A × B Example
If these two bits is 00, plus 0
If these two bits is 01, plus A
If these two bits is 10, 2A 2A = 4A-2A plus
If these two bits is 11, then add 3A 3A = 4A-A
If these two bits is 11, then the Save A, 4A to be lower fill time, since the partial product has the right by two, plus the original number 4A becomes plus A
How do I know there are operating. 4A?
Two bits to 10 or 11, then add 4A
A high speed multiply member - Array Multiplier
Conventional design suitable hardware multiplier is "serial shift" method and "concurrent addition" combination
, this method does not require many components.
After slow serial method, however, performed at least one time multiplication is performed n times a time of addition,
not meet the requirements for high-speed scientific and technical multiplication raised. Since the advent of large scale integrated circuits, high-speed cell array multiplier came into being, there have been various forms of
pipelined array multiplier
, they belong to the parallel multiplier, providing great speed. Array Multiplier calculation process is as follows:
First: When the multiplier digit is a 1, the value of multiplicand we placed directly place. Appropriately position after the operation done by the first few bits of the multiplier and multiplicand are put in the position.
Second: When the digits of the multiplier is zero, we can place the proper position 0, as a partial product.
Third: We use pen and paper to calculate multiplication, using an AND gate to implement in hardware. For example: in 1000 × 1, multiplier and multiplicand bit 1 of each individual have to do with the operation, the result of 1000 is the result we want. It can be seen that we can just use the door to complete the multiplication we want.
Fourth: After completion of the operation the partial products are used to complete the addition of the final result of the multiplication operation.
The above description of four points, we can use the simplest and most intuitive way to describe the fixed-point multiplier circuit is described. We do a partial product using the AND operation, the use of full adder (Full adder) to compute the final result of the partial product. FIG. There is a 5x5 fixed point multiplier sign bit architecture shown in FIG.
1. Analysis of the merits of the serial adder
• Does not require a lot of simple devices, hardware architecture;
• too slow to perform a multiplication operation time is at least n times the addition operation;
Since approximately one third of all multiplication arithmetic operation, so that high-speed multiplying member is necessary.
2. The array multiplier unsigned
It provided two binary unsigned integers A = am-1 ... a1a0, B = bn-1 ... b1b0
Their values are a and b, namely:
(1) calculation method used to process:
(2) without sign multiplier logic block diagram of an array
(3) 5 X 5 array of unsigned multiplier bit is not logic circuit
3. The array multiplier unsigned
(1) 2 complement circuit
Example 1: 1010 complement.
Example 2: 1011 complement.
Method:
From the start of the rightmost number a0, from right to left until it finds the first "1
", for example, ai = 1, 0≤i≤n. Thus, each input to AI bits are left negated, i.e., 1 to 0, 0 to 1.
2 circuit for complementing
A multiplier array (2) with symbol A
(3) Structure:
Including complement multiplier stage yet complemented array multiplier symbol.
In such a logical structure, using a total of three complement control:
• two front complement operator is acting:
the two operands A and B before the multiplication is unsigned multiplier array (core member), to become a positive integer.
• the complement operator is acting:
when the two inputs are inconsistent symbol operands, the operation result into a signed number.
After the necessary complement operation, code values of A and B is supplied to the n × n-bit unsigned array multiplier, and thereby generate 2n-bit product:
A · B = P = p2n-1 ... p1p0 p2n = an⊕bn wherein P2n is the sign bit.
Third, the division point
Division algorithm design
With n bits fractional fixed:
Dividend x, which is the original code [x] Original = xf. Xn-1 ... x1 x0
Divisor y, which is the original code [y] Original = yf. Yn-1 ... y1 y0
There are commercially q = x / y, which is the original code [q] original = (xf⊕yf) + (0. xn-1 ... x1x0 / 0.yn-1 ... y1y0)
•'s symbolic computation qf = xf⊕yf the same as the original code multiplication;
• numerical computation part of business, in essence, is the quotient of two positive operation.
1. hand count calculating step
Example: Let dividend x = 0.1001, the divisor y = 0.1011, imitation decimal division, the process of seeking hand count of x ÷ y.
X ÷ y obtained quotient q = 0.1101, and the remainder is r = 0.00000001.
2. Different machine operation and the hand count
An original code division
The same result and hand calculation, but the remainder of the remainder is not a true
,
multi-ride the 2n, it is correct remainder should be 2n × rn, namely: 0.00000001
(1) In the computer, the decimal point is fixed and can not be simply calculated using the hand approach. For ease of machine operation,
the divisor Y fixed, the remainder and dividend for the left (corresponding to x 2).
(2) the machine will not mental arithmetic, we must first subtract, if the remainder is positive, and they knew enough to cut; if the remainder is negative, cut enough to know. The remainder must restore the original cut is not enough to continue operations down. This method is called the recovery remainder method.
(3) To restore the original remainder, plus as long as the remainder of the current divisor can be. However, due to restore the remainder, so that the division process is performed the number of steps is not fixed, and therefore the control is more complex.
In practice commonly used non-restoring method, also known as addition and subtraction alternative methods. Characterized during operation if there is not enough Save, the need to recover the remainder The remainder symbols, operation may continue downward, but the fixed number of steps, the control is simple.
3. Restore the remainder Act
Subtracting the number of dividend, when reduced enough, supplier 1; when not commercially Save 0.
As the provider 0:00 if not enough reduction that can not subtract, but now at 0:00 judgment whether business, has reduced the divisor, in order to be able to correct the next operation, must have been added back to lose divisor recover the remainder. This is the "
recovery remainder method
."
[Example 1] x = 0.1001, y = 0.1011, find x / y-restoring method used.
Solution: [x] = the original [X] Complement = x = 0.1001, [y] fill = 0.1011, [-y] = 1.0101 complement
Every time equivalent to the remainder left by 2, obtained after the n-bit quotient, multiplied by the equivalent of more than 2 ^ n, so the last remainder should be multiplied by 2 ^ (- n) is the correct value.
Therefore: [q] = the original 01,101 remainder [R4] 0 = original.
0000
0001
4. subtraction alternating method (non-restoring method)
Since the above-restoring process to restore the remainder, so that the division of the number of steps is not fixed, the control is more complex. It is actually used
subtraction alternative methods.
Features: situation occurs when enough Save operation process, it is unnecessary to restore the remainder, but according to the sign of the remainder, to continue down the operation, so a fixed number of steps, the control is simple.
Operation rules:
When the remainder is positive, the quotient 1 with a remainder left one, the number of deduction;
When the remainder is negative, the quotient 0, the remainder left one, plus the divisor.
[Example 2] x = 0.1001, y = 0.1011, find x / y alternate addition and subtraction method Solution: [x] Original = [x] Complement = x = 0.1001, [y] fill = 0.1011, [- y] up. = 1.0101
[Example 3] x = 0.1011, y = 0.1101, find x / y alternate addition and subtraction method Solution: [x] Original = [x] Complement = x = 0.1011, [y] fill = 0.1101, [- y] up. = 1.0011
The original code division flowchart subtraction alternately
Subtraction principle primitive logic diagram of alternative methods
Array divider
Divider array is a parallel arithmetic unit, large scale integrated circuit manufacturing. Compared with earlier serial divider, the divider array only required less control lines, and can provide satisfactory high-speed operation speed.
There are various forms divider array:
Non-restoring divider array;
Complement divider array and the like.
1. The controllable adder / subtractor (CAS) unit
Pipeline division for parallel logic array.
Relationship CAS input and output unit can be used as a set of logic equations represented by:
Si = Ai⊕ (Bi⊕P) ⊕Ci
Ci + 1 = (A + C) · (Bi⊕P) + AICI
• When P = 0, that we are familiar with a full adder (FA) of the formula:
Si = Ai⊕Bi⊕Ci
Ci + 1 = AiBi + + Here whip
• When P = 1, then differencing have the formula:
In the case where the subtraction: an input referred borrow input Ci, Ci + 1 is called the borrow output.
To illustrate the actual realization of the internal circuit unit CAS, the equation
Si = Ai⊕ (Bi⊕P) ⊕Ci
Ci + 1 = (A + C) · (Bi⊕P) + AICI
Be converted, the form can be obtained:
In these two expressions, each of the three can use a combinational logic circuit (including the inverter) is achieved. Therefore the delay time for each of the basic units of 3T CAS unit.
2. not restored remainder divider array (array of non-restoring division, also called subtraction alternating method.)
In non-restoring division of the array: • The remainder when the number is positive (ri ≥ 0), supplier "1", the next subtraction operation, complement arithmetic subtraction is implemented to 2, in which case
[XY] Complement = [x] Complement + [-y] up;
• When the remainder is negative (ri <0), quotient "0" next time do an addition operation;
• After each operation you want to complete the remainder left one, then do the divisor addition or subtraction; • sign by the sign's number two position by summing together.
Example: x = 0.101001, y = 0.111, find x ÷ y. [-Y] Complement = 1.001
Example: x = 0.100101, y = 0.101, find x ÷ y. [-Y] Complement = 1.011
• x is a 6-bit dividend decimal (double-length value):
ｘ＝0.ｘ1ｘ2ｘ3ｘ4ｘ5ｘ6
It is composed of the input vertical line and the top line on the diagonal to the rightmost provided.
• y is a divisor of three decimal places
y = 0.y1y2y3
It is into this array in a diagonal direction. This is because:
In the left portion of the remainder of the division of the number required, the following equivalent operations can be used instead: Let remainder held stationary i.e., diagonally to the right and the divisor.
• the top row of the initial operation performed often subtraction. Thus the control line in the top row of P is fixed to "1."
• complement arithmetic subtraction is implemented to 2, then the feedback line on the right end of each of the CAS cells used as the initial carry input.
Carry output leftmost cell of each line • determine the value of the business.
The current feedback to the next line of business, we will be able to determine the operation of the next line.
Due to carry-out signal indicative of the sign of the current partial remainder, therefore, will determine the operation of the next line will be an addition or subtraction.
Seen from the figure, the array flow divider is composed of an array with a controllable adder / subtractor (CAS) means to achieve.
Extended to the general case:
A (n + 1) bit in addition to (n + 1) bit array by the subtraction of alternating division (n +1) 2 th CAS units, wherein the two numbers (dividend and divisor) are positive operation. n is the number of bits mantissa.
An array of non-restoring divider for,
during operation:
• along each line has a carry (or borrow) propagation;
• simultaneously on all rows they carry chain is a serial connection;
• CAS delay time of each unit cell is 3T.
Thus, to a 2n-bit by n-bit non-restoring array divider, the number of cells is (n + 1) 2, considering signal delay in the maximum case, which divide execution time is
td = 3T (n + 1)
^ 2 where n is the number of bits mantissa.
