According to JEDEC eMMC 5.1 and experience painstakingly organized, paid content, reprinting is prohibited .
The column " Yuan Takes You to Learn: Detailed Explanation of the eMMC Protocol "
The full text is 2700 words, and the key point is to master the device identification process (CMD1 -> CMD2 -> CMD3), which is very commonly used and the place where abnormalities are most likely to occur. Just understand other things. The main contents are:
Table of contents
1.2 Access mode validation (higher than 2GB of densities)
1.4 Device identification process
1 Device identification mode
In device identification mode, the host resets the device, verifies the operating voltage range and access mode, identifies the device and assigns the device a relative device address (RCA) on the bus. All data communication in device identification mode uses the command line (CMD) only.
1.1 Device Reset Device Reset
After the device receives the GO_IDLE_STATE command (the parameter is Ox00000000), it enters the Idle state. In addition to this way, there are some other ways to enter Idle State.
- After completing the Boot operation
- In the Pre Idle state, the CMD line is pulled down for 74 Cycle
- After power on (if there is no enable Boot Operation)
Then start after power-up. In this state, the output bus driver of the device is in a high-impedance state, and the device is initialized to a default relative device address (Ox0001) and a default driver stage register setting. The master recognizes the clock rate as the bus clock. CMD0 whose parameter is Ox00000000 is valid in all states except Inactive State. In Inactive State, the device does not accept CMD0 with parameter 0x00000000. For reasons of backward compatibility, if the CMDO parameter received by the device is not OxFFFFFFFA or OxFOFOFOFO, in the non-Inactive state, the device regards it as a device reset command and enters the Idle state. The CMDO with the parameter OxFFFFFFFA is a boot command in the Pre-boot state, but if the host issues this command in any state other than the Inactive state and the Pre-boot state, the device will treat it as a reset command and Move to Idle state, CMD0 is a soft reset, eMMC device will not restart.
1.2 Access mode validation (higher than 2GB of densities)
When the device is busy, the e-MMC device responds with a fixed mode of 0x00FF 8080 or 0x40FF 8080. When the device enters the Ready state, the response fixed mode is Ox80FF8080 (capacity less than or equal to 2GB) or OxCOFF8080 (capacity greater than 2GB), and does not enter the Inactive state.
1.3 From Busy to Ready
The busy bit in the CMD1 response can be used by the device to tell the host that it is still going through its power-up/reset process and is not ready to communicate yet. In this case, the master must send CMD1 repeatedly until the busy bit is cleared. During the initialization process, the host is not allowed to change the operating voltage range and access mode settings. These changes will be ignored by the device. If the operating conditions do change, the host must reset the device (using CMDO with parameter Ox00000000) and restart the initialization process. However, for devices that have been inactive, a hard reset must be done by powering off and then on. The command GO_INACTIVE_STATE (CMD15) can be used to send the address device to the inactive state. Use this command when the host explicitly specifies to deactivate a device. Command CMD1 shall be executed by all devices defined by this standard.
1.4 Device identification process
After the bus is activated, the host will send ( CMD1 ) to the device, and the device needs to return CMD1 Ready within 1s.
In practice, mobile phones often fail to boot , mostly because the device cannot return to CMD1 Ready . In this case, an exception occurs during the eMMC power-on initialization process, such as data corruption or metadata error that causes the card to be locked.
The host issues a broadcast command ALL_SEND_CID ( CMD2 ), requesting all devices to provide their unique device identification (CID) numbers. All unidentified devices (i.e. those in the ready state) simultaneously start sending their CID numbers sequentially. If the output CID bit of these devices does not match the corresponding bit on the command line in any one bit period, then stop sending CID immediately and must wait for the next identification cycle (keep in Ready state). Since each device's CID number is unique, only one device should successfully send its full CID number to the host. Then, the device enters the recognition state.
The host issues CMD3 (SET_RELATIVE_ADDR) to assign a relative device address (RCA) to the device, which is shorter than the CID and will be used to ping the device in future data transfer modes (usually with a higher clock rate than 0). addressing. Once the RCA is received, the device state changes to the standby state and the device does not respond to further identification cycles. Additionally, the device switches its output driver from open-drain to push-pull. As long as the host receives the response (CID) to its identification command (CMD2), it repeats the identification process, that is, the cycle of CMD2 and CMD3. If no more "devices" respond to this command, all devices have been recognized. The timeout condition for the completion of the identification process is that there is no start bit more than N clock cycles after sending CMD2.
2 interrupt mode
The interrupt mode on the e-MMC system enables the master (e-MMC host) to continuously transfer data to the slave (device). This mode reduces the polling load on the host, thereby reducing the power consumption of the system, while keeping the host sufficiently responsive to device service requests. Support for e-MMC interrupt mode is an option for both host and device. Before the host issues the GO_IRQ_STATE (CMD40) command, it must ensure that the device is in the standby state. The host must keep the clock signal active while waiting for an interrupt response from the device. The clock rate may vary depending on the required response time. The host sets the device to interrupt mode using the GO_IRQ_STATE (CMD40) command. A device in the wait-irq state is waiting for an internal interrupt to trigger an event. Once an event occurs, the device starts sending a response to the host. This response is sent in open-drain mode. While waiting for an internal interrupt event, the device is also waiting for a start bit on the command line. Once the start bit is detected, the device will abort interrupt mode and switch to standby state.
Regardless of winning or losing bus control during the CMD40 response, the device switches to standby (as opposed to CMD2). When the host receives the interrupt response, the host returns to the standard data communication process.
If the host wishes to terminate the interrupt mode before receiving an interrupt response, it can generate a CMD40 response (Device bit = 0) by itself using the reserved RCA address Ox0000; this will bring the device back from the waiting irq state to the standby state. The host can now resume standard communication procedures.
Disclaimer :
This article is organized based on public information and aims to introduce more storage knowledge. The articles contained in the article are only the author's opinion and do not constitute investment or commercial advice. This article is only for learning and communication, not for commercial use. If you have any questions or infringements, please contact the author.