Common concepts related to ZYNQ

common abbreviations

ZYNQ : It is a new generation of All Programmable System-on-Chip (APSoC) launched by Xilinx, which perfectly integrates the software programmability of the processor and the hardware programmability of the FPGA.

PS : (Processing System), ZYNQ can be roughly divided into two parts: ARM and FPGA. PS is the SOC part of ARM, which is the processing system of the whole board.

PL : (Progarmmable Logic), which means programmable logic, which is the FPGA part on ZYNQ.

MIO : (Multiuse I/O), a multi-function IO pin, if you have learned the microcontroller, you can understand it as pin multiplexing, which belongs to the PS part, which is the ARM part. It is worth mentioning that the MIO signal is invisible to the PL part, so the operation on the MIO can be regarded as a pure PS operation.

EMIO : (Extendable Multiuse I/O), expandable multi-function IO pin, still belongs to the PS part, but connected to the PL, and then connected from the PL pin to the outside of the chip to realize data input and output. If MIO is not enough, PS can control the pin of PL part by driving EMIO. EMIO has 64 pins at our disposal.

APU : (Application Processor Unit), application processor unit, used to be used by AMD to refer to accelerated processing units (Accelerated Processing Units), but the meaning is completely different on ZYNQ, pay attention to the distinction. The APU contains dual ARM-CortexA9 cores, plus high-speed buffering, DMA, timers, interrupt control, floating point and NEON co-processing, which can be understood by analogy to the MCU in the 51 single-chip microcomputer and the MPU on the STM32 of the Cortex-M series.

But there is still a saying about the name of APU. Without M, it means that it intends to get rid of the name of the microprocessor Micro. It is not easy to replace it with Application. It means that applications can be run on it, implying that this system needs full-scale operation. systematic.

TTC : (Triple Time Counter), literal translation is triple time counter, in fact, there are 3 independent channels in this counter, which can count independently. Hang on the APB to provide timing or counting services for the system or peripherals.

WDT : There are two watchdog timers, which are used to monitor ARM-Cortex A9 respectively. If the software runs away and cannot clear the timer, the watchdog will be reset after a period of time. Generally, it is useless. When I was learning STM32, I felt that this function is quite powerful. It can always monitor whether the program runs away. Later, I found that the chance of running away is too small. The stability of the current board is very good, so that I have not seen it now. I have seen that the watchdog works, but it is also a risk protection.

SWDT : System-level watchdog timer, the clock and reset signal of this watchdog can come from outside the chip, so that even if the system has a serious failure, such as the clock frequency itself has problems, it can still pass through irrelevant to the system. The external signal counts, and resets when the count is full.

SCU : (Snoop Control Unit), used to maintain the consistency of the data cache between the dual cores, two ARM-Cortex A9, if one writes to storage, it is only written into the cache, not into the main memory, if the second A9 reads The operation involves the first dirty data segment, and the SCU must ensure that the second A9 cache has the latest data. The existence of the SCU makes the two cores interconnected into a "dual core" to become an MPsoc.

Introduction to ZYNQ

The essential feature of ZYNQ is that it combines a dual-core ARM Cortex-A9 processor with a traditional field-programmable gate array ( FPGA ) logic unit. Since the programmable logic part of this new device is based on the 7 series FPGA of Xilinx 28nm process, "7000" is added to the name of this series of products to maintain consistency with the 7 series FPGA, and it is also convenient for future development of this series of FPGAs. Product naming.

In the past, the term SoC was often used to refer to Application Specific Integrated Circuit (ASIC).

Programmable System-on-Chip (SOPC, System-on-Progammable-Chip) provides a more flexible solution for the above applications: a SoC implemented on a programmable, reconfigurable chip. Among them, the programmable chip refers to the FPGA.

Compared with SOPC, ZYNQ provides a more ideal platform for flexible SoC: Xilinx makes it "All-Programmable System-on-Chip (APSoC, All-ProgrammableSoC)". It perfectly integrates the software programmability of the processor with the hardware programmability of the FPGA to provide unparalleled system performance, flexibility and scalability.

On ZYNQ, ARM Cortex-A9 is an application-level processor that can run an operating system like Linux, and the programmable logic is based on the FPGA architecture of the Xilinx7 series. The ZYNQ architecture implements the industry-standard AXI interface, enabling high-bandwidth, low-latency connections between the two parts of the chip. This means that the processor and logic can each be used to their best advantage without incurring the overhead of interfacing between two discrete devices.

Introduction to ZYNQ PL

ZYNQ PL part is equivalent to Xilinx 7 series FPGA

The simplified FPGA basic structure consists of 6 parts

1. Programmable I/O Unit

2. basic programmable logic unit

   The basic programmable logic unit is the main body of programmable logic, and its internal connection and configuration can be flexibly changed according to the design to complete different logic functions. FPGA is generally based on SRAM technology, and its basic programmable logic unit is almost composed of look-up table (LUT, LookUpTable) and register (Register). The internal lookup table of Xilinx7 series FPGA has 6 inputs , and the lookup table generally completes pure combinational logic functions . The FPGA internal register structure is quite flexible, and can be configured as a flip-flop with synchronous/asynchronous reset or set, clock enable, or as a latch. FPGA relies on registers to complete synchronous sequential logic design .

   The more classic configuration of the basic programmable logic unit is a register plus a look-up table, but there are certain differences between the registers and the look-up table of different manufacturers, and the combination modes of the register and the look-up table are also different.

   Altera's programmable logic unit is usually called LE (LogicElement), which consists of a register plus a LUT. Most FPGAs of Altera organically combine 10 LEs to form a larger functional unit - logic array module (LAB, LogicArrayBlock). In addition to LE, LAB also includes carry chains between LEs, LAB control signals, local interconnect line resources, LUT cascade chains, register cascade chains and other connection and control resources.

   The programmable logic unit in Xilinx 7 series FPGA is called CLB (Configurable Logic Block, configurable logic block). Each CLB contains two logic slices (Slice). Each Slice consists of 4 lookup tables, 8 flip-flops and some other logic.

A CLB is the smallest component of a logic unit, arranged as a two-dimensional array in the PL, connected to other similar resources through a programmable interconnect. Each CLB contains two logic slices and is adjacent to a switch matrix

3. Embedded Block RAM

   At present, most FPGAs have built-in block RAM (BlockRAM). FPGAs are embedded with programmable RAM modules, which greatly expands the application range and flexibility of FPGAs.

4. Routing Resources

   The wiring resources connect all units inside the FPGA, and the length and process of the connection determine the driving capability and transmission speed of the signal on the connection. There are abundant wiring resources inside the FPGA chip.

5. underlying embedded functional unit

   The concept of the underlying embedded functional unit is relatively general. Here we refer to those embedded functional modules with a high degree of generality, such as PLL (PhaseLockedLoop), DLL (DelayLockedLoop), DSP, CPU, etc.

6. Embedded dedicated hard core

   The embedded dedicated hard core here is different from the previous underlying embedded unit. The embedded dedicated hard core mentioned here mainly refers to those with relatively weak versatility. Not all FPGA devices include hard cores.

   On the PL side of ZYNQ, there is a digital-analog hybrid module - XADC, which is a hard core. The XADC contains two analog-to-digital converters (ADCs), an analog multiplexer, on-chip temperature and on-chip voltage sensors, and more. We can use this module to monitor chip temperature and supply voltage, and can also be used to measure external analog voltage signals.

ZYNQ PL Architecture

Introduction to ZYNQ PS

ZYNQ is actually a processor-centric system, and PL is just one of its peripherals. The highlight of the Zynq-7000 series is that it contains a complete ARM processor system, and the processor system integrates a memory controller and a large number of peripherals, so that the Cortex-A9 processor can be completely independent of the programmable logic unit. And in fact, in ZYNQ, the power supply circuits of PL and PS are independent, so that the PS or PL part can be powered off if it is not used.

The processor built using the programmable logic resources of FPGA is called "soft core" processor, and its advantage lies in the number of processors and the flexibility of implementation.

Integrated in ZYNQ is a "hard-core" processor, which is a dedicated and optimized hardware circuit on a silicon chip. The advantage of a hard-core processor is that it can obtain relatively high performance. In addition, the hardware processor and soft-core processor in ZYNQ do not conflict. We can use PL logic resources to build a Microblaze soft-core processor to work with the ARM hard-core processor.

In the Zynq processor system, there is not only the ARM processor, but also a set of related processing resources, forming an application processing unit (Application Processing Unit, APU), as well as extended peripheral interfaces, cache memories, memory interfaces, interconnect interfaces and clocks generating circuit, etc.

The schematic diagram of the ZYNQ processor system (PS) is shown below, where the red highlighted area is the APU.

1. APU

The APU is mainly composed of two ARM processor cores, each of which is associated with some computational units: a NEONTM media processing engine (MediaProcessingEngine, MPE) and a floating point unit (FloatingPointUnit, FPU); a memory management unit (MemoryManagementUnit , MMU); and a first-level cache memory (divided into two parts, instruction and data). There is also a secondary cache memory in the APU, and then there is an on-chip memory (OnChipMemory, OCM), which are shared by the two ARM processors. Finally, a consistency control unit (SnoopControlUnit, SCU) forms a bridge connection between the ARM core and the secondary cache and OCM memory. The SCU is also partially responsible for connecting with the PL, and this interface is not marked in the figure.

2. external interface

The Zynq PS implements numerous interfaces, both between the PS and the PL , and between the PS and external components . The communication between the PS and the external interface is mainly realized through multiplexed input/output (MultiplexedInput/Output, MIO) , which provides 54 pins that can be flexibly configured, which indicates that the mapping between external devices and pins can be defined on demand. When it is necessary to expand more than 54 pins, it can be realized by **extending MIO (ExtendedMIO, EMIO)**. EMIO is not a direct path between PS and external connections, but by sharing the I/O resources of PL to achieve.

3. memory interface

   The memory interface unit on the Zynq-7000APSoC consists of a dynamic memory controller and several static memory interface blocks. The dynamic memory controller can be used for DDR3, DDR3L, DDR2 or LPDDR2. The static memory controller supports a NAND flash interface, a Quad-SPI flash interface, a parallel data bus, and a parallel NOR flash interface.

4. on-chip memory

   On-chip memory includes 256kB of RAM (OCM) and 128kB of ROM (BootROM). OCM supports two 64-bit AXI slave interface ports, one port is dedicated to CPU/ACP access through APUSCU, while the other is shared by PS and all other bus masters in PL. BootROM is a non-volatile memory on the ZYNQ chip, which contains the drivers for configuration devices supported by ZYNQ. BootROM is invisible to the user and is reserved exclusively for the booting process.

5. AXI interface

   ZYNQ tightly combines high-performance ARMCotex-A series processors and high-performance FPGAs in a single chip, which brings many advantages to the design, such as reducing size and power consumption, reducing design risks, and increasing design flexibility. After merging processors and FPGAs with different process characteristics on one chip, the interconnection path between the on-chip processor and FPGA becomes the top priority of ZYNQ chip design. If the data interaction between CotexA9 and FPGA becomes a bottleneck, then the performance advantages of the combination of processor and FPGA cannot be brought into play.

   Xilinx uses the AXI protocol to connect IP cores from the Spartan-6 and Virtex-6 series. In the 7 series and ZYNQ-7000 AP SoC devices, Xilinx continues to use the AXI protocol in the IP core. The full English name of AXI is Advanced eXtensible Interface, which is an advanced extensible interface. It is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol proposed by ARM.

   The AXI protocol is a high-performance, high-bandwidth, low-latency on-chip bus with the following characteristics:

   1. The address/control and data channels of the bus are separated
   2. Support for unaligned data transfers
   3. Support burst transmission, only the first address is needed during burst transmission;
   4. have separate read/write data channels;
   5. Support significant transfer access and out-of-order access;
   6. Easier timing closure.