Some parameter descriptions in makefile

#obj = main.o sub.o add.o div.o mul.o
src = $(wildcard *.c) #Search
for .c files and add paths

obj = $(patsubst %.c, %.o, $(src)) #Character
matching and replacement, replace all .c suffixed strings in src with .o suffixed strings

target = app

#target :dependency
$(target):$(obj)
　　gcc $^ -o $@
　　#gcc $(obj) -o $(target)

%.o:%.c
　　gcc -c $< -o $@

# $<: The first dependency in the rule
# $^: All dependencies in the rule
# $@: The target in the rule

#Anonymous target prevents name collision.PHONY
:clean
clean:
rm $(obj) $(target) -f

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