80x86 system registers and system instructions
1. Flag register (EFLAGS)
The meaning of the flag bits of the flag register EFLAGS is as follows:
TF bit 8 is the trace flag, which, when set, enables single-step execution for debugging operations. Single stepping is disabled on reset. In single-step execution, the processor will generate a debug exception after each instruction is executed, so that we can observe the state of the executive program after each instruction is executed.
I/O Privilege Level field when IOPL bits 13-12. This field indicates the I/O privilege level IOPL of the currently running program or task. The CPL of the current task or program must be less than this IOPL to access the I/O address space. Only when the CPL bit privilege level is 0, the program can use the POPF or IRET instruction to modify this field. IOPL is also one of the mechanisms to control the modification of the IF flag.
NT bit 14 is the Nested Task flag. It controls the link between the interrupted task and the calling task. The processor sets this flag when executing a task call using a CALL instruction, interrupt, or exception, and checks and modifies this NT flag when returning from a task via an IRET instruction. This flag can also be modified using the POPF/POPFD instructions, but changing the state of this flag in the application will generate unexpected exceptions
Resume Flag when RF bit 16. This flag is used to control the processor's response to breakpoint instructions. When set, this flag temporarily disables breakpoint instructions from generating debug exceptions; when the flag is reset, breakpoint instructions generate exceptions. The main function of RF is to allow re-execution of an instruction after debugging an exception. When the debugging software uses the IRETD instruction to return to the interrupted program, the RF flag in the EFLAGS content on the stack needs to be set to prevent the instruction breakpoint from causing another exception. The processor will automatically clear the flag after the instruction returns, thereby allowing the instruction to break again. point exception.
VM bit 17 is the virtual-8086 mode flag. When the flag is set, the virtual-8086 mode is newly turned on. When the flag is reset, it returns to protected mode.
memory management registers
The processor provides four memory management registers (GDTR, LDTR, IDTR and TR) for specifying the base address of the system table used by segmented memory management, which contains important information about the segmentation mechanism. GDTR, IDTR and LDTR are used to address the segment that stores the descriptor table, and TR is used to address a special task state segment TSS (Task State Segment). The TSS segment contains important information about the currently executing task. See the figure below, the processor provides specific instructions for loading and saving these registers.
1. Global Descriptor Table Register (GDTR)
The GDTR register is used to store the linear base address (32 bits) and table length value (16 bits) of the Global Symbol Description Table (GDT). The base address specifies the address of byte 0 in the GDT table in the linear address space, the table length specifies the byte length value of the GDT table, and the instructions LGDT and SGDT are used to load and save the contents of the GDTR register, respectively. Just after the machine is powered on or the processor is reset, the base address is set to 0 by default, and the table length is set to 0xFFFF. China must load a new value for GDTR during protected mode initialization.
2. Interrupt descriptor table register IDTR
Similar to the role of GDTR, the IDTR register is used to store the 32-bit linear base address and 16-bit table length value of the interrupt descriptor table. Instructions LIDT and SIDT are used to load and save the contents of the interrupt descriptor table, respectively. After the machine is just powered on or the processor is reset, the base address is set to 0 by default, and the length value is set to 0xFFFF
3. Local descriptor table register LDTR
LDTR is used to store the 32-bit linear base address, 16-bit segment limit and descriptor attribute value of the local descriptor table LDT. The instructions LLDT and SLDT are used to load and save the segment descriptor portion of the LDTR register. The segment containing the LDT table must have a segment descriptor entry in the GDT table
4. TR task register
The TR register is used to store the 16-bit segment selector of the current task TSS segment, the 32-bit base address, and the 16-bit segment length and descriptor attribute value. It refers to a TSS type in the GDT table into the descriptor, and the instructions LTR and STR are used to load and save the segment selector part of the TR register, respectively.
control register
控制寄存器（CR0、CR1、CR2、CR3）用于控制和确定处理器的操作模式以及当前执行任务的特性，见下图，CR0中含有控制处理器操作模式和状态的系统控制标志；CR1保留不用，CR2含有导致也错误的线性地址；CR3中含有页目录表物理内存基地址，因此该寄存器也被称为页目录基地址寄存器（PDBR）
1、CR0中协处理器控制位
CR0中的4个bit位：扩展类型位ET、任务切换位TS、仿真位EM和数学存在位MP用于控制80x86浮点（数学）协处理器的操作。
ET是CR0的位4是扩展类型标志，当该标志为1时，表示指明系统有80387协处理器存在，并使用32位协处理器协议。当ET=0指明使用80287协处理器。如果仿真位EM=1，则该位将被忽略。在处理器复位操作时，ET会被初始化指明系统中使用的协处理器类型。如果系统中有80387，则被设置为1，否则若有一个80287或没有协处理器，则ET被设置为0
TS是CR0的第3位，是任务已切换（Task switched）标志，该标志用于推迟保存任务切换时的协处理器内容，直到新任务开始实际执行协处理器指令。处理器在每次任务切换时都会设置该标志，并且执行协处理器指令时测试该标志。
如果设置了TS标志并且CR0的EM标志为0，那么在执行任何协处理器指令之前会产生一个设备不存在（DNA）异常。如果设置了TS标志，但没有设置CR0的MP和EM标志，那么执行协处理器指令WAIT/FWAIT之前不会产生设备不存在异常。如果任务从没有使用过协处理器，那么相应协处理器上下文就不用保存了。
EM是CR0第2位，仿真标志，当该位置设置时，表示处理器没有内部或外部协处理器，执行协处理器指令时会引起设备不存在异常；当清除时，表示协同有协处理器，设置这个标志可以迫使所有浮点指令使用软件来模拟。
MP是CR0的位1是监控协处理器标志（Monitor coprocessor或math present）标志，用于控制wait/fwait指令与TS的交互作用。如果MP=1、TS=1，那么WAIT指令将产生一个设备不存在异常。如果MP=0，则TS标志不会影响WAIT的执行
2、CR0中保护控制位
PE CR0的位0是启用保护标志，当设置该位时，即开启了保护模式；当复位时即进入实地址模式。这个标志仅开启段级保护，而并没有启用分页机制。若要启用分页机制，那么PE和PG标志都要置位
PG CR0的位31时分页标志位，当设置该位时即开启了分页机制；当复位时则禁止分页机制，此时所有线性地址等于物理地址。在开启此标志之前必须已经或同时开启PE标志；即若要分页机制，则PE与PG标志都要设置
WP对于Intel 80486或以上的cpu，CR0的16位是写保护标志，当设置该标志时，处理器会禁止超级用户程序（例如特权等级0的程序）向用户级只读页面执行写操作；当该位复位时，则反之。该标识有利于unix类操作系统在创建进程时实现写时复制技术。
NE对于Intel 80486或以上的CPU，CR0的位5是协处理器错误（Numberic Error）标志。当设置该标志时，就启用了X87协处理器错误的内部报告机制；若复位该位，那么就使用PC形式的X87协处理器错误报告机制。当NE为复位状态并且CPU的IGNNE输入引脚有信号时，那么数学协同处理器X87错误将被忽略
启用保护模式PE位和开启分页PG位分别用于控制分段和分页机制
CR2和CR3
CR2和CR3用于分页机制，CR3含有存放页目录表页面的物理地址