Computer real mode and protected mode

Computer real mode and protected mode

real mode

In the original 8086 processor, there were a total of 14 registers, all of which were 16 bits. Namely AX, BX, CX, DX, SP, BP, SI, DI, IP, FLAG (PSW), CS, DS, SS, ES. These 14 registers are divided into general registers, control registers and segment registers in a certain way. The address bus of the 8086 is 20 bits, which can support addressing up to 1MB, but the 16-bit register can only access the address space of 64KB, so how can we access the address of 1MB in the 16-bit register? So the idea of ​​segmentation is introduced, that is, the method of segment register: IP is adopted. First shift the address in the segment register to the left by 4 bits to indicate which segment the address I want to access is in, and then add the offset in the IP register to determine the code address to be accessed. Specifically,
in order to solve this problem, when the 8086 processor forms a physical address, it first shifts the contents of the segment register to the left by 4 bits (equivalent to multiplying by 10 in hexadecimal, or 16 in decimal) to form a 20-bit segment address , and then add it to the 16-bit offset address to get a 20-bit physical address. For example, for the logical address F000H:052DH, when forming the physical address, the processor shifts the segment address F000H to the left by 4 bits to become F0000H, and then adds the offset address 052DH to form the 20-bit physical address F052DH.
　　In this way, because the segment register is 16 bits, the 1MB memory can be divided into 65536 segments at most under the condition that the segments do not overlap. An address consists of two parts: segment and offset. The calculation formula of the physical address is:
physical address (physical address) = segment register (segment) * 16 + offset (offset)
, where both segment and offset are 16 bits.

protected mode

The initial program addressing is the direct "segment: offset" mode. The advantage of this is that what you see is what you get. The address specified by the programmer is the physical address, and the physical address is visible to the programmer. But precisely because of this, the code is not protected. It is precisely because of this that there is a protected mode. In protected mode, what is stored in the segment register is no longer the real address of the segment, but the segment selector. The segment we want to access is located through the segment selector. There are 2 bits in the segment selector representing the privilege level, and 1 bit representing Whether to access the GDT table or the LDT table. In addition, the upper 13 bits are the index subscript, which indicates that the data or code to be accessed is in the index subscript of the GDT (Global Segment Descriptor), through which the segment descriptor is located, and then the base address of the segment is obtained from the segment descriptor , and then add the offset to locate the address of the segment to be accessed. In GDT, a segment descriptor has a total of 8 bytes. Then it means that the GDT table can hold up to 2 to the 13th power, that is, 8192 segment descriptors. The two bits representing the privilege level, 0 represents the kernel state, and 3 represents the user state, which represents the current CPL. That is, the privilege level of the current code segment or data segment. In the segment descriptor, there is also a corresponding privilege level, which is DPL. In non-conforming code, if the CPL is greater than the DPL, it proves that there is no access right, and a GP exception is reported, which forms a certain protection.

Through the above knowledge, in real mode, the segment base address is directly placed in the segment register, and now it is used to access the corresponding descriptor to obtain the segment base address and other information. In this way, will the access speed slow down? Woolen cloth? In order to solve this problem, each segment selector of the 386 has an 88-bit (8*8+24) wide segment descriptor cache register that is invisible to the programmer (that is to say, the programmer cannot directly manipulate it). . Whenever the content of the segment register is changed, as long as the privilege level is reasonable, the corresponding 8-byte descriptor in the descriptor table will be automatically taken out of the descriptor table and loaded into the cache register (and 24 bits other content). Once loaded, subsequent access to that segment will use the descriptor information of the cache register instead of fetching it from the table again, which greatly speeds up the execution time, as shown in the following figure

Since the contents of the segment descriptor cache register are reloaded only when the selector is reset, when you modify the descriptor selected by the selector, you must reload the corresponding selector. In this way, 88 The contents of the Bit Descriptor Cache will not change. However, when the value of the selector changes, the processor automatically loads the invisible part.

Let's talk about the steps to address a memory operand when there is no paging operation:

1. Load 16 digits into the segment selector, and give a 32-bit address offset (such as CS:IP) at the same time, then go to the base address of the GDT stored in the GDTR.

2. According to the index value, TI and RPL value in the segment selector, and then according to the segment address and segment limit in the corresponding descriptor table register, a series of legality checks (such as privilege level check, limit check) are performed. There is no problem with this segment. Take out the corresponding descriptor and put it into the segment descriptor cache register.

3. The 32-bit segment base address in the descriptor is added to the 32-bit effective address placed in EIP, etc., to form a 32-bit physical address.

Note: In protected mode, the 32-bit segment base address does not have to be shifted to the left by 4 bits, but is directly added to the offset to form a 32-bit physical address (as long as it does not overflow). The advantage of this is that the segment does not have to be located at an address that is divisible by 16, nor does it need to be left shifted by 4 bits and then added.