register
- The CPU of the x86-64 structure contains a set of 16 general-purpose registers that store 64-bit values; the first registers in history were only 8 8-bit registers, and later went through 16-bit, 32-bit and now 64-bit, and the registers are also Expanded from 8 to 16.
- The program can use 8 bits, or 16 bits, or 32 bits, or 64 bits according to the name of each register; the use of each register has an agreed purpose.
The names and usage of registers are given in the form of a table below
| 63 | 31 | 15 | 7 | 0 |
|---|---|---|---|---|
| %rax | %eax | %ax | %al | return value |
| % rbx | %ebx | %bx | % bl | callee saves |
| %rcx | % ecx | %cx | %cl | 4th parameter |
| %rdx | %edx | %dx | %dl | 3rd parameter |
| %rsi | % is | %and | % sil | 2nd parameter |
| % rdi | %I know | %Of | %the heart | 1st parameter |
| % rbp | %ebp | %bp | % bpl | callee saves |
| %rsp | %esp | %sp | %spl | stack pointer |
| % r8 | % r8d | % r8w | %r8b | 5th parameter |
| %r9 | %r9d | %r9w | %r9b | 6th parameter |
| % r10 | % r10d | %r10w | %r10b | caller save |
| %r11 | %r11d | %r11w | %r11b | caller save |
| %r12 | %r12d | %r12w | % r12b | callee saves |
| %r13 | %r13d | %r13w | %r13b | callee saves |
| % r14 | %r14d | %r14w | %r14b | callee saves |
| %r15 | %r15d | %r15w | %r15b | callee saves |
Note: %rip is the program counter, different from these 16.
- The caller save means that when the P function calls the Q function, the contents of the register are saved by the caller P, and Q can directly use the register.
- The callee save means that when the P function calls the Q function, the contents of the register are saved by the callee Q. Before using these registers, Q should first store the values in these registers on the stack, and before Q returns, it should be stored. Restore the corresponding value from the stack to the register.
type of data
The following are the corresponding data types on 64-bit structures. Intel uses the term "word" to refer to a 16-bit data type; byte refers to bytes, long word refers to 32 bits, and q refers to 64 bits.
| C statement | Intel data type | assembly code suffix | size (bytes) |
|---|---|---|---|
| char | byte | b | 1 |
| short | Character | w | 2 |
| int | double word | l | 4 |
| long | four characters | q | 8 |
| char * | four characters | q | 8 |
| float | single precision | s | 4 |
| double | double precision | l | 8 |
cpu addressing
To operate data, the CPU needs to know the address of the data, which is achieved by addressing. Addressing is divided into direct addressing and indirect addressing. Here are some explanations.
Operands:
- literal $ integer in standard C notation
- register R[ra]
- memory reference Mb[Addr]
Imm(rb, ri, s): effective address Imm+R[rb]+R[ri]* s; Note that both rb and ri must be 64-bit registers, and the scale factor s must be 1, 2, 4 or 8
| Types of | Format | operand value | name |
|---|---|---|---|
| immediate | $Imm | Imm | immediate addressing |
| register | out | R [ra] | register addressing |
| memory | Imm | M[Imm] | absolute addressing |
| memory | (out) | M [R [ra] | indirect addressing |
| memory | Imm(rb) | M[Imm+R[rb]] | (base address + offset) addressing |
| memory | (rb, ri) | M[R[rb]+R[ri]] | Indexed addressing |
| memory | Imm (rb, ri) | M [Imm + R [rb] + R [ri]] | Indexed addressing |
| memory | (, ri, s) | M [R [ri] * s] | Scaled Indexed Addressing |
| memory | Imm (, ri, s) | M [Imm + R [ri] * s] | Scaled Indexed Addressing |
| memory | (rb, ri, s) | M[R[rb]+R[ri]*s] | Scaled Indexed Addressing |
| memory | Imm (rb, ri, s) | M[Imm+R[rb]+R[ri]*s] | Scaled Indexed Addressing |
No operation can directly modify data from memory to memory. To realize data operation from memory to memory, you can only modify the data to the register first, and then modify it to the memory through the register.