Early chipsets are usually divided into two bridges to control the communication between components, namely
North Bridge: Responsible for connecting components such as CPUs, memory sticks and graphics cards with high speed;
South Bridge: Responsible for connecting devices with slower speeds, such as hard drives, USB, network cards, etc.
But the CPU needs the support of the North Bridge to read and write to the main memory. That is, the CPU needs to communicate with the main memory, which will divide the total available bandwidth of the north bridge.
So, this South Bridge and North Bridge is the previous concept again, and now there is no South Bridge and North Bridge. In the process of upgrading the Core 2 to the 7th generation, the chip architecture has undergone tremendous changes. The high-speed components such as the memory controller and PCIE controller originally in the north bridge were integrated into the CPU, while the remaining functions of the north bridge were integrated into the original south bridge, and there was no north bridge on the motherboard.
The Southbridge has also made a lot of cuts, including cutting out the PCI controller. So you see that there are PCI slots on the new motherboard, which are provided by third-party chips, and they are no longer called South Bridge, but are called PCH chipsets.
So the CPU is divided into two parts, one part is called core, which, as the name suggests, is the computing core part of the CPU. The other part is called uncore, which includes bus controller, cache controller, cache, memory controller, PCIE controller and so on. The PCH chip is connected to the CPU through the DMI bus.
QPI is the bus connecting the CPU core and the uncore. And FSB (Front Side Bus, Front Side Bus) is the bus connecting the old CPU and the North Bridge. Because both ends of the QPI connection are in the CPU, the efficiency is actually very high, much higher than the FSB.
The structure in the chipset is PCIE controller, disk controller, USB2.0 root device, and the latest may have USB3.0 root device.
Front Side Bus (FSB)
The name "front-side bus" is a concept proposed by AMD when it launched the K7 CPU, but it has always been misunderstood by everyone that this term is just another name for FSB. Generally speaking, the FSB refers to the speed of the connection between the CPU and the motherboard. This concept is based on the oscillation speed of the digital pulse signal, and the speed of the front-side bus refers to the speed of data transmission. Since the maximum bandwidth of data transmission depends on It depends on the width and transmission frequency of all simultaneously transmitted data, that is, data bandwidth = (bus frequency × data bit width) ÷ 8.
A bus is a hardware channel that connects a computer's microprocessor to memory chips and the devices that communicate with it. The front side bus connects the CPU to main memory and peripheral buses to system components such as disk drives, modems, and network cards.
People often describe the bus frequency in MHz. The difference between FSB and front-side bus frequency: the speed of the front-side bus refers to the speed of data transmission, and the FSB is the speed of synchronous operation between the CPU and the motherboard. That is to say, 100MHz FSB means that the digital pulse signal oscillates 100 million times per second; and 100MHz FSB means that the acceptable data transmission amount of CPU per second is 100MHz×64bit=6400Mbit/s=800MByte/s (1Byte=8bit). The front side bus supported by the motherboard is determined by the chipset and generally has sufficient backward compatibility. For example, if the 865PE motherboard supports 800MHz front side bus, the front side bus of the installed CPU can be 800MHz or 533MHz, but it will not be able to play the full effect of the motherboard.
32-bit and 64-bit CPU and front bus width
The transfer speed between the memory controller within the CPU and the memory (front-side bus speed) measures the maximum amount of data that the memory can provide to the CPU. • The memory also has a clock, and the limit of this clock is also determined by the memory controller in the CPU.
For example, the working clock of the memory controller to the memory can reach up to 1600MHz, and generally the amount of data transmitted each time is 64 bits, and this 64 bits is the 'width'. Therefore, the fastest bandwidth that the CPU can get from the memory is 1600MHz*64bit=1600MHz*8Bytes=12.8GBytes/s.
The amount of data that the CPU can process each time is called the word size, which is divided into 32-bit and 64-bit. What is now called a 32- or 64-bit computer is divided according to the word size. The early 32-bit CPU can parse a limited amount of data each time, so the amount of data transmitted from memory is also limited, which results in a 32-bit CPU that can only support up to 4GBytes of memory.