Personal knowledge about the structure of the chip STM32F407
1. The internal structure of the chip (not go into) *
kernel is equivalent to our computer's CPU, which via a bus matrix and Flash, SRAM, etc. are connected. And peripherals FLASH, RAM and the sheet, these features are arranged in a common 4GB address space (i.e., memory), we programming, operation and it is these features.
Then we will not help thinking, memory is how to Flash, SRAM allocation of space it?
Memory Map
The memory itself has no address information, its address is assigned by the chip manufacturer or the user, the memory allocated to the process is called memory-mapped address
In this 4GB address space, ARM has broad-brush evenly divided into eight blocks, 512MB each 
of which has three blocks that we should pay attention to, is the Block0, Block1, Block2, the above is what we are talking about Flash, SRAM and the peripheral block is located, which is visible in a different sub-blocks.
Flash (that is where our code is stored) in Block0, the address is 0x0800 0000 ~ 0x080F FFFF (1MB) , as to what Block0 other storage areas that we do not get to the bottom.
And the address allocation for Block1 
Block2 for the peripheral chip design, according to the different peripheral speeds of the bus, is divided into Block2 APB and AHB
two parts, which has been divided into APB1 APB and APB2 and, AHB and into AHB1 AHB2
in this area of the memory Block2, design is on-chip peripherals, they need to four bytes as a unit, a total of 32bit, each corresponding to a different function unit, when we drive controlling these peripheral units may work, on-chip peripheral bus is divided into four, according to the different peripheral speeds, different bus mounted peripherals of different , low mount the APB peripherals, the AHB mount high-speed peripherals. The base address of the corresponding address bus of the lowest we called the bus, the bus is also mounted on the base address of the first address bus peripherals. In which the peripheral bus address on APB1 lowest piece from here, also known as peripheral base address.
Because APB1 wherein the first peripheral strip is Block2 bus, its address is the base address bus, the address is offset relative to the base 0
And other peripherals and how to assign this four buses do?
Within each bus address range assigned different peripherals, mounted on different buses according to the speed required for the various peripherals, e.g. mount AHB1 GPIO bus peripheral.
So peripherals mount after the bus, within its address range, and the distribution of what?
The answer is to register (we can according to the different functions of each unit in order to function in the name of the memory unit to take an alias, this alias is what we often say that the register, this unit has been allocated to the memory-addressed with particular capabilities alias the process is called register map)
In an example GPIOF, GPIOF address is 0x4002 1400 ~ 0x4002 17FF
has distributed control register in the peripheral address range
(GPIO there are many registers, each with a specific function. Each register 32bit, accounting four bytes are arranged in order of the peripheral base address, location register to be described are offset relative to the peripheral base address)
register function is to control the state of the peripherals, for example, a high level or a low, open drain or push-pull outputs, etc., with each register their unique features.
Then we will think that we have to control peripherals to find its address, and then locate the address of the register to be used, it is not very trouble?
This requires us to register with the c language encapsulates
the next time we go into the details again, this time just to talk about my personal knowledge of the structure of the chip in some places may not rigorous enough well written, hope forgive me, my big two students, the first to write technical blog.
Here is my mind mapping
