1. LCD control principle
The S5PV210 processor has its own LCD controller, which controls the display of the LCD and transfers the LCD image data from a video buffer located in the system memory to an external LCD driver interface.
Type :
1. STN (Super Twisted Nematic), which is characterized by low power consumption, but insufficient brightness and long response time; (1602 type)
2. TFT (Thin Film Transistor), which is characterized by short response time and long response time Clear, but the power consumption is slightly higher, (this type should be used in my own experiments, and this type is used as a computer liquid crystal display device).
3. LTPS (low temperature polysilicon), superior performance in all aspects, but high technical requirements;
4. OLED (Organic Light Emitting Diode) has superior performance in all aspects, but high technical requirements.
- RGB interface: ((24-bit parallel, 8-bit serial) I use it myself)
- indirect-i80 interface
- UV interface
- RGB (1BPP to 24BPP)
- YCbCr 4:4:4 (local bus only)
1: The relationship between the display screen and the memory.
We have all bought graphics cards and know that it is better to buy discrete graphics cards, so why is independent graphics better? What
is the difference between independent graphics and integrated graphics?
Features of independent display : There is an independent memory
that can copy content independently (DMA controller)
Features of integrated display : Shared memory with the motherboard
can copy content independently (DMA controller)
2: Why can the screen be displayed? (Integrated display)
1) During initialization, a space opened up in the memory is used as video memory
2) The content to be displayed is written to the video memory
3) The lcd controller reads the video memory, and then writes it into the display screen.
A: DMA completes the transmission of display data, and does not require the CPU to execute the COPY function
B: The LCD controller provides timing signals, video data, ......
Second, LCD display principle
If you need to display a full screen of data, the size of the data: 800*480*24bits
1. Frame synchronization signal : LCD refresh frequency, vertical synchronization signal frequency, field frequency
Frame synchronization signal = 50Hz~70Hz, typical value: 60Hz
2. Frequency of line sync signal : how many lines are there in a frame?
The frequency of the line synchronization signal = (480 + the number of lines retraced (45)) * the frequency of the frame synchronization signal
3, the frequency of the pixel clock: the frequency of scanning pixels
Pixel clock frequency = (800 + the retraced pixels in one line (256)) * frequency of line sync signal
1. The higher the division frequency of the LCD screen, the higher the frequency of
VCLK. 2. The maximum upper limit of the frequency of VCLK: HCLK_DSYS=166MHz
3. Thinking: What is the maximum LCD screen that can be connected to S5PV210?
Calculation:
In 800*480 LCD, the frequency value of VCLK:
VCLK = (800+256)*(480+45)*60Hz = 33.264MHz
3. Description of LCD parameters (selection of LCD screen)
1. The number of pixels in the row and column of the resolution
. 2. The length of the diagonal of the display area with an effective size , in inches.
3. How many bits of data is used for a pixel to describe the color position ----24bits
4. Response time refresh time---->60Hz (16ms)
response time----> a few ms
5. Brightness cd/m** 2 ---> Highlight screen: 600
Normal screen: 250
6. Contrast white brightness / black brightness.
7. Life unit: hour 50,000 hours
When the brightness of the LCD screen is reduced to half of the factory brightness, it is considered that the life is over.
8. The viewing angles of the four directions are asymmetrical, and generally one direction is relatively poor
Fourth, the design interface of the hardware
1. Interface of S5PV210 LCD controller
RGB interface signal :
LCD_HSYNC : line synchronization signal, indicating the beginning of a line of data, after the LCD controller shifts the entire horizontal line (whole line) data into the LCD driver,
Insert an LCD_HSYNC signal;
LCD_VSYNC : frame synchronization signal, indicating the beginning of a frame of data, the LCD controller inserts an LCD_VSYNC signal immediately after a complete frame is displayed,
Start the display of a new frame; the frequency of the VSYNC signal indicates how many frames of images can be displayed in one second, which is called "display frequency"
LCD_VCLK : pixel clock signal, indicating that the data of one pixel is being transmitted;
LCD_VDEN : data enable signal ;
LCD_VD[23:0] : LCD pixel data output port
Five, inch LCD screen interface
0xffff
Bits 1-11 are functions, and the remaining eight bits are blue, green, and red respectively.
8. What is the main purpose of the LCD driver?
1. Set the LCD controller according to the specific parameters of the LCD screen (interface, bpp, ......)
2. Set the frequency of the synchronization signal of the LCD screen (VCLK, VSYNC, HSYNC .....)
3. Set Timing parameters of the LCD screen (frame retrace time, line retrace time, sync signal polarity...)
4. Set the location and size of the video memory
Nine, LCD timing diagram
1. Output timing of LCD controller
(1) Frame transmission process
1) When the VSYNC signal is valid, it indicates the beginning of a frame of data, and the signal width is (VSPW + 1) HSYNC signal cycles, that is, (VSPW + 1) invalid lines;
2) After the VSYNC signal pulse , a total of (VBPD + 1) HSYNC signal cycles are required before the valid line data appears; therefore, after the VSYNC signal is valid, (VSPW + 1 + VBPD + 1) invalid lines must be passed;
3) Immediately issue (LINEVAL + 1) rows of valid data;
4) Finally (VFPD + 1) invalid rows;
(2) Transmission process of pixel data in a row
1) When the HSYNC signal is valid, it indicates the beginning of a row of data, and the signal width is (HSPW + 1) VCLK signal cycles, that is, (HSPW + 1) invalid pixels;
2) HSYNC signal After the pulse, it takes (HBPD + 1) VCLK signal cycles before valid pixel data appears;
3) Then send out (HOZVAL + 1) pixels of valid data;
4) Finally (HFPD + 1) invalid pixels;
(3) After the time parameters of VSYNC, HSYNC, VCLK and other signals are set, and the address of the frame memory is told to the LCD controller, it can automatically initiate DMA transfer to obtain image data from the frame memory, and finally in the above signal. Appears on the data bus VD[23:0] under control. The user only needs to write the image data to be displayed into the frame memory.
