1. The computer system is designed from the middle. What does the middle refer to? What are the benefits of this design?
Answer: "Intermediate" refers to the interface between software and hardware in a multi-level hierarchy, which is currently between the traditional machine level and the operating system machine level. Such a design can reasonably allocate the functions of software and hardware, optimize the design of software and hardware, provide more and better hardware support for software and applications, enable software and hardware to be designed at the same time, and shorten the design cycle of the system.
"Start in the middle" design idea: "In the middle" refers to the soft and hard interface in the hierarchy. Consider not only the available hardware devices, but also what support the hardware provides for the implementation of the operating system and the compilation system, and then design software and hardware from the middle point upwards and downwards respectively. The advantages are: in view of the defects of the above two methods, the software and hardware are designed in parallel, which shortens the system design time, and the software and hardware functions can be modified according to the actual situation in the design process, and the interaction is good.
2. Consider a two-level Cache : the first-level Cache is L1 , and the second-level Cache is L2 .
( 1 ) Assume that in 1000 memory accesses, L1 misses 40 times and L2 misses 20 times. Find various local miss rates and global miss rates.
( 2 ) Assuming that the hit time of L2 is 10 clock cycles, the miss cost of L2 is 100 clock cycles, the hit time of L1 is 1 clock cycle, and each instruction accesses memory 1.5 times on average, regardless of the impact of write operations. Q: What is the average fetch time? What is the average stall time per instruction in clock cycles?
Solution (1) The miss rate (global and local) of the first-level Cache is 40/1000 , or 4% ; the local miss rate of the second-level Cache is 20/40 , or 50% ; the global cache of the second-level Cache The miss rate is 20/1000 , or 2% .
(2) Average memory access time = hit time L1 + miss rate L1 × (hit time L2 + miss rate L2 × miss cost L2 ) = 1 + 4% × ( 10 + 50% × 100 ) = 1 + 4 %×60 = 3.4 clock cycles
Since each instruction is fetched 1.5 times on average, and the average stall time of each fetch is: 3.4 - 1.0 = 2.4
So, the average stall time per instruction = 2.4 x 1.5 = 3.6 clock cycles.