Eight Tips for Solving FPGA Timing Problems
Advice 1. If the timing difference is not much, within 1NS, it can be done by modifying the synthesis and placement and routing options. If it is much worse, you have to move the code.
Advice 2. Look at the timing report, pick a path with the tightest timing, and look carefully at what causes it. First, what is the logic level? Which circuit has the problem, the multiplier or the RAM interface data to figure out where the problem is first
Advice 3. Inserting registers is the kingly way to optimize timing, but it depends on the specific situation. It is not necessary to insert registers. If the effect of inserting registers is not obvious, first check the position where the registers are inserted. If the registers are not inserted in the middle of the critical path, but At one end, it's really not that obvious.
Advice 4. Find out the critical path, look at the timing report, and see what causes the frequency to not go up. If the combinational logic is complex, optimize the logic or copy the logic. If the DSP delay is large, choose a multi-stage pipeline, as long as If you want to get 150, you can.
Advice 5. When looking at the timing report, it is recommended to look at the circuit diagram at the same time, which is the most intuitive
Advice 6. Compare the code, draw the circuit diagram of the part involved in the critical path, and then calculate how many registers to insert and where to insert according to the timing requirements.
Advice 7. For 32BIT comparators, the carry chain is a bit long. You can compare them in sections and divide them into 4 8BIT data sections for comparison, or you can divide them into two sections, first compare the high 16, insert the register, and then compare the low 16, the timing is very good , if you want to go deeper, write a comparator by yourself, don't adjust the library.