Recent project development needs to learn Altera's incremental compilation, so I have done some learning and recorded some of my personal insights here. The following conclusions may be wrong or refuted. I hope that the gardeners will discuss and make progress together after reading, and please give me more advice.
Altera's incremental compilation is mainly to set partition and logicock two regional planning to work together. Partition is a logical block division, that is, our entire project is logically divided into different modules, each module is connected by an interface, and the internal logic of the modules is independent of each other. Logiclock is the division of physical blocks, that is, the division of the actual resource area of the chip during the layout and routing process of our project. The two block divisions are independent, logiclock focuses on the planning of the placement and routing stage, and patition focuses on the planning of logic synthesis. Therefore, the combination of the two will have a very significant effect.
The basic idea of specific collaborative use should be the same: first, divide the whole project logically. In the quartus software, we can set the partition through the project level in Project Navigator>>Hierarchy; then we can set the partition according to the pin assignment The situation, the usage of PLL, different modules are divided into different actual chip areas in the chip planner for layout and routing; after the setting is completed, we will compile the project. At this time, we can export the partition set before, which is equivalent to our own customization. For the IP core, only the interface has no internal logic, and there are many export modes. The most commonly used one is post-fit, that is, the logic and layout are completely fixed, so that we can fully guarantee the timing optimization results when transplanting to a large project.
Personally, in the design process, the main functions of incremental compilation are as follows:
- When the project is large, each module is designed independently, and finally integrated and imported, each independent module is set as an incremental compilation partition, and the system design is combined with the LogicLock physical area division to ensure the independent optimization results of each module;
- When the project compilation time is long, the part that does not need to be changed is set to the incrementally compiled partition, and the type is changed to the post-fit type. When the source code is not changed, it will not take time to recompile the wiring. Takes less time to synthesize and place and route;
- When doing timing optimization, combining incremental compilation can sometimes speed up the efficiency of timing optimization.
Here is mainly a brief talk about the understanding of incremental compilation, without in-depth discussion of the use and settings of the software.
Here are a few details for future use:
Option settings for exporting partitions. As shown in the figure below, the export partition has the following options. The meaning of each option is checked or not:
- If only post-synthesis is checked, the exported modules only have the results of synthesis, excluding the results of layout and routing;
- If only post-fit is checked, the exported module contains the comprehensive results and the layout results only;
- Check post-fit and check ecxport routing at the same time, the exported module contains the results of synthesis and the results of layout and routing; it should be noted here that post-fit contains the results after the fitter, and the fitter includes placement (layout) and The result of routing.
In the process of importing a partition, you need to choose a conflict resolution method.
- The conflict here is mainly for the conflict between the placement and routing results contained in the imported partition module and the logiclock area restrictions that may exist in the destination project to be imported. That is to say, the physical area of the planned module reserved in our project does not match the physical area of the layout and routing actually included in the partition to be imported, resulting in a conflict.
In this project, in order to save compilation time, when setting partition and post-fit type setting, if the source code has not changed, the software will not be compiled and wired, but once the source code is changed, the layout and wiring will still be performed again.