1. Application background
1.1 Causes of metastability
In the FPGA system, if the T su and Th of the flip-flop are not satisfied during the data transmission , or the recovery time of the release of the reset signal relative to the effective clock edge during the reset process is not satisfied, metastable may occur. At this time, the output terminal Q of the flip-flop is in an indeterminate state for a long period of time after the valid clock edge. During this time, the Q terminal is in an oscillating state between 0 and 1, rather than equal to the data input terminal D. value. This period of time is called the resolution time. After the resolution time, the Q terminal will stabilize to 0 or 1, but it will stabilize to 0 or 1, which is random and has no necessary relationship with the input.
1.2 Metastable Occurrence Occasions
As long as there are asynchronous components in the system, metastability is unavoidable, and metastability mainly occurs in common designs such as asynchronous signal detection, cross-clock domain signal transmission, and reset circuits.
1.3 Metastability hazards
After the metastable state is generated, the output of the Q terminal of the register may be a burr, oscillation, or a fixed voltage value before it stabilizes. The metastable state in the signal transmission will cause other digital components connected to it to make different judgments, some judged to "1", some judged to "0", and some also entered the metastable state, the digital components will Logical confusion. Metastability in the reset circuit may cause reset failure. How to reduce the probability of metastability has become a consideration that needs to be paid attention to in FPGA design.
2. Theoretical Analysis
2.1 Metastability in signal transmission
In a synchronous system, the input signal is always synchronized with the system clock, which can meet the timing requirements of the register, so metastability does not occur. Metastability problems usually occur in some cross-clock domain signal transmission and asynchronous signal acquisition.
They happen for the following reasons:
(1) When the signal is transmitted across the clock domain, since the phase shift of the source register clock and the destination register clock is unknown, the source register data sends data, and the data may arrive at the destination register of the asynchronous clock domain at any time, so it cannot be guaranteed to satisfy the destination register Tsu. and the requirements of Th;
(2) In the asynchronous signal acquisition, since the asynchronous signal can reach the destination register at any point in time, it cannot be guaranteed to meet the requirements of the destination registers Tsu and Th;
When the data changes in the Tsu-Th time window of the destination register, that is, when the setup time or hold time of the data is not satisfied, the metastable phenomenon may occur. As shown in Figure 3.1.
Figure 3.1 Schematic diagram of metastable state generation
It can be seen from the figure that there will be an oscillation period of Tmet (decision time) after the Tco time after the metastable state is generated. When the oscillation ends and returns to a stable state, it will be "0" or "1", which is random. Therefore, it will affect the subsequent circuit judgment.
2.2 Metastability of reset circuit
2.2.1 Asynchronous reset circuit
In the reset circuit design, the reset signal is basically asynchronous. The commonly used asynchronous reset circuit Verilog is described as follows:
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) a <= 1’b0;
else a <= b;
end
The integrated reset circuit model is shown in Figure 3.2:
Figure 3.2 Asynchronous reset circuit model
As shown in Figure 3.3, it is the reset timing diagram of the reset circuit. If the cancellation time of the asynchronous reset signal is within the Trecovery (recovery time) and Tremoval (removal time), it will inevitably cause a metastable state, and the output will oscillate after the Tco of the clock edge, and the oscillation time is Tmet (determination time). ), and eventually stabilize to "0" or "1", which may cause reset failure.
Figure 3.3 Asynchronous reset timing
2.2.2 Metastability of synchronous reset circuit
In the reset circuit, because the reset signal is asynchronous, some designs use a synchronous reset circuit to reset, and most of the data do not think that metastability will occur in the synchronous reset circuit. Steady-state, but the probability is less than the asynchronous reset circuit.
As described in the verilog code below for the synchronous reset circuit.
always @(posedge clk)
begin
if(!rst_n) a <= 1’b0;
else a <= b;
end
The integrated hardware circuit is shown in Figure 3.4.
Figure 3.4 Synchronous reset circuit
Here, we do not discuss the resource consumption of synchronous reset, but only discuss the generation of metastable state of synchronous reset.
When the input terminal Din is at a high level, and the cancellation time of the reset signal is within the Tsu and Th of clk, the metastable state occurs. As shown in the sequence of Figure 3.5, when the reset cancellation time is within Tsu and Th of clk, the input data is "1", and the data after passing and the input data are also within Tsu and Th of clk, so it is bound to cause similar Metastable conditions for asynchronous signal acquisition.
Figure 3.5 Timing diagram of synchronous reset circuit
2.3 Metastability generation probability and crosstalk probability
In actual FPGA circuit design, people often think about how to reduce the influence of metastable state on the system, but few people consider how to reduce the probability of metastable state and the probability of metastable crosstalk.
2.3.1 Probability of metastable state
It can be seen from the above analysis that the metastable state of the system occurs because the Tsu and Th of clk are not satisfied, or the removal and recovery time of the reset signal is not satisfied. Tsu+Th of common FPGA devices is about 1ns, and the sum of reset removal and recovery time is about 1ns.
When the asynchronous signal is not a set of data, or the semaphore is small, it is necessary to perform synchronous processing on the asynchronous signal, such as collecting an asynchronous pulse signal. As long as the pulse signal changes within the clock Tsu and Th windows, it is very likely A metastable state will occur, and the probability of metastable state generation is approximately:
Probability = (Setup Time + Hold Time) / Acquisition Clock Period (Equation 3-1)
It can be seen from Equation 3-1 that as the frequency of clk increases, the probability of metastable state increases.
For example, if the system uses a 100M clock to collect an external signal, and the collection clock period is 10ns, the probability of a metastable state in the collection is: 1ns/10ns = 10%
Similarly, if a 300M clock is used to collect an external signal, the probability of generating a metastable state is: 1ns/3.3ns = 30%
If an external signal is collected with a clock with a three-phase phase difference of 120°, the probability of metastable state is close to 90%
Therefore, in the process of asynchronous signal acquisition, in order to reduce the probability of metastability:
(1) Reduce the system working clock and increase the system period, the probability of metastable state will be reduced;
(2) FPGAs with better technology are used, that is, FPGA devices with smaller Tsu and Th times;
2.3.2 Crosstalk probability of metastability
When using asynchronous signals, a good design will process the asynchronous signals synchronously. Generally, multi-level D flip-flops are cascaded for synchronization. As shown in Figure 3.6, three-level D flip-flops are used to synchronize asynchronous signals.
Figure 3.6 Three-level register synchronization
Most of the data of this model say that after the first-level register generates metastable state, the probability of stable output of the second-level register is 90%, and the probability of stable output of the third-level register is 99%. If it is passed on, it will directly collapse the system with weak self-repairing ability. Next, we analyze the probability of this crosstalk.
As shown in Figure 3.7, metastable state occurs in a normal first-level register, and the second-level and third-level registers eliminate the metastable timing model.
Figure 3.7 Three-level register eliminates metastability
As can be seen from the above figure, when the first register is metastable, after the oscillation of Tmet is stabilized, the second register can collect a stable value. But why is the second-level register still possible to generate metastable?
Because the oscillation time Tmet is affected by many factors, the Tmet time is long or short, so when the Tmet time is longer than one acquisition period, the second-level register will acquire metastable state. As shown in Figure 3.8.
Figure 3.8 Secondary register metastability
As can be seen from the above figure, the second level is also a metastable state, so in this case, the metastable state generates crosstalk, which is transmitted from the first level register to the second level register, and may also crosstalk from the second level register to the second level register. The third level register. In this way, the design logic will be judged incorrectly, resulting in metastable transmission, which may cause the system to crash and crash.
2.3.3 Metastable oscillation time Tmet
The metastable oscillation time Tmet is related to the acquisition and stability of the post-stage registers. The influencing factors of Tmet include: the production process of the device, the temperature, the environment, and the time when the register is collected from the metastable state from the stable state. Even some specific conditions, such as interference, radiation, etc., will cause Tmet to increase.
3. Application Analysis
If there is a metastable state, we need to eliminate the metastable state. There are three ways to eliminate the metastable state:
(1) Synchronous processing of asynchronous signals;
(2) FIFO is used to buffer data communication across clock domains;
(3) The reset circuit is handled by asynchronous reset and synchronous release.
3.1.1 Synchronous edge extraction for asynchronous signals
In the process of asynchronous communication or cross-clock domain communication, the most commonly used is to perform synchronous extraction edge processing on asynchronous signals. Extracting the rising edge of an asynchronous signal usually uses the procedure shown in Listing 4.1.
Listing 4.1 Bipolar register fetch edge
input sig_nsyn;
wire sig_nsyn_p;
reg [1: 0] sig_nsyn_r;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) sig_nsyn_r <= 2’d0;
else sig_nsyn_r <= {sig_nsyn_r [0], sig_nsyn};
end
assign sig_nsyn_p = sig_nsyn_r [0] & ~ sig_nsyn_r [1];
This edge extraction method is not suitable for a stable system. For example, when the first-level register acquires a metastable state, it will inevitably cause the sig_nsyn_p output to be metastable, which will cause the circuit that uses the sig_nsyn_p signal to judge. Influence, and even judge the wrong value.
According to the generation probability of metastable state in section 3.3.1, if the first-level register is planted at 100M, the probability of generating metastable state is about 10%. As the system acquisition frequency increases, the probability of generating metastable state is also will rise accordingly. Therefore, when the asynchronous signal cross-frequency extraction edge is performed, one more level register is generally used to eliminate the metastable state. In the case of high system stability requirements, more levels of registers are used to eliminate the metastable state, as shown in program listing 4.2 As shown, in order to eliminate the metastable state by adopting the 4-level register, the corresponding edge signal is generated two clock cycles later.
Program listing 4.2 Multi-level register extraction edge signal
input sig_nsyn;
wire sig_nsyn_p;
reg [3: 0] sig_nsyn_r;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) sig_nsyn_r <= 2’d0;
else sig_nsyn_r <= {sig_nsyn_r [2 :: 0], sig_nsyn};
end
assign sig_nsyn_p = sig_nsyn_r [2] & ~ sig_nsyn_r [3];
3.1.2 FIFO for asynchronous cross-frequency data processing
When the data flow is from one clock domain to another clock domain, FIFO is used as the intermediate buffer in most cases, and the occurrence of metastability can be avoided by using dual clocks to buffer the data.
3.1.3 Asynchronous reset, synchronous release
For the metastable state in the case of reset, it is often caused by insufficient recovery time and removal of the clock. Therefore, the most common processing method is to use asynchronous reset and synchronous release. Common circuit models are shown in Fig. The second-level register output is used as the global reset signal output.
Listing 4.3 Asynchronous reset handling
wire sys_rst_n;
reg [1:0] rst_r;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) rst_r <= 2’d0;
else rst_r <= {rst_r[0], 1’b1};
end
assign sys_rst_n = rst_r[1];
Processing asynchronous signals, asynchronous data, and asynchronous resets in the above three ways can effectively improve the stability of the system. Reduce the generation of metastable states.
Quoted from: http://www.cnblogs.com/linjie-swust/archive/2012/01/07/YWT.html