STM32 terminal priority, I have read a lot and feel that this is straightforward and easy to understand

Transferred from Wildfire "Fun with STM32 with Zero Dead Ends"

 

1. Preemption Priority and Response Priority

    The interrupt vector of STM32 has two attributes, one is the preemption attribute, the other is the response attribute, and its attribute number

The smaller the value, the higher the priority.
    Preemption refers to the property of interrupting other interrupts, that is, because of this property, there will be nested interrupts (interrupted
by interrupt B in the process of executing interrupt service function A, and then continue to execute interrupt service function after interrupt service function B is executed.

A), the preemption attribute is configured by the parameter of NVIC_IRQChannelPreemptionPriority.

    The response attribute is applied when the preemption attribute is the same. When the preemption priority of the two interrupt vectors is the same,
if two interrupts arrive at the same time, the interrupt with the higher response priority will be processed first. The response attribute is
configured by the NVIC_IRQChannelSubPriority parameter. For example, there are now three interrupt vectors, as shown in the table below.


    If the kernel is executing the interrupt service function of C, it can be interrupted by interrupt A with a higher preemption priority. Since B
and C have the same preemption priority, C cannot be interrupted by B. But if the B and C interrupts arrive at the same time, the kernel
will respond first to the B interrupt with a higher priority.

2. When configuring the priority of the NVIC priority group
    , pay attention to a very important issue, that is, the number of interrupt types. NVIC
can configure the priority of 16 kinds of interrupt vectors, that is to say, the number of preemptive priority and response priority is determined by a 4-
digit number, and the number of digits of this 4-digit number is allocated as preemptive priority part and Response priority section. There are 5 groups of
assignments :
 Group 0: All 4 bits are used to configure the response priority. That is, 16 interrupt vectors have different response priorities
.
 Group 1: The highest 1 bit is used to configure the preemption priority, and the lower 3 bits are used to configure the response priority. Indicates that there are 2
levels of preemption priority (level 0, level 1), and there are 8 response priorities, that is, among the 16 interrupt vectors, there are
8 interrupts, and their preemption priorities are all 0, and their The response priorities are 0~7, the preemption priorities of the other 8 interrupt
vectors are all 1, and the response priorities are 0~7.
 Group 2: 2 bits are used to configure the preemption priority, and 2 bits are used to configure the response priority. That is, 4 kinds of preemption priority
level, 4 response priorities.
 Group 3: The upper 3 bits are used to configure the preemption priority, and the lowest 1 bit is used to configure the response priority. That is, there are 8 kinds of preemption
priorities, 2 kinds of response 2 kinds of priorities.
 Group 4: All 4 bits are used to configure the preemption priority, that is, the 16 interrupt vectors configured by the NVIC are only

Preemptive attribute, no response attribute.

 

    To configure these priority groups, the library function NVIC_PriorityGroupConfig() can be used, and the input parameters are NVIC_PriorityGroup_0 ~ NVIC_PriorityGroup_4, which are the five allocation groups described above.
    Therefore, some readers are puzzled. With such a powerful STM32, all GPIOs can be configured as external interrupts, and peripherals such as USART and ADC also have interrupts, while NVIC can only configure 16 interrupt vectors, so more than 16 interrupt vectors are used in a project. What about an interruption? Note that NVIC can configure 16 interrupt vectors instead of 16. When there are more than 16 interrupt vectors in the project, there must be more than two interrupt vectors that use the same interrupt type, but have the same interrupt type. cannot be nested within each other.

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