CPU interrupt
- A total of 14 CPU interrupts (INT1~INT14)
- Among them, 12 CPU interrupts are connected to peripheral interrupt expansion, and each CPU interrupt can be divided into eight peripheral interrupts.
- So a total of 12X8=96 interrupt sources
Schematic diagram of peripheral interruption
Multiplexing of Interrupts Using the PIE Block
- The CPU has 12 interrupts, but each interrupt can be expanded into eight peripheral interrupts (x is 12 CPU interrupts)
- Peripheral interrupt source
- interrupt vector table
- PIE interrupt flag register (Latch is generated when an interrupt occurs, and the interrupt bit is locked in this place)
- PIE Interrupt Enable Register
- When PIEACK is 0, it means that the CPU is ready to receive interrupts before the interrupt can be sent to the CPU layer
- interrupt flag register
- interrupt enable register
- Global interrupt mask bit (the last level, set to 0 will be sent to the CPU)
Interrupt Path Flowchart
- Any peripheral or external interrupt including PIE interrupt source, and its own peripheral interrupt module can also be enabled.
- PIE recognizes INTx.y, and the bit of PIE interrupt is latched, PIEIFRx.y=1.
- When the interrupt is to be sent to the CPU layer by the PIE, two conditions must be established.
- PIEIERx.y=1
- PIEACKx to be cleared to 0
- When 3(a) and 3(b) are true, the interrupt is sent from the PIE to the CPU layer. At this time, you should realize that PIEACKx is set to 1, indicating that other interrupts in the group can be sent from the PIE to the CPU.
- The CPU interrupt flag register will LATCH interrupt and display 1
- It will be passed to the CPU after Enable
- Only when the CPU interrupt mask bit is set to 0 can an interrupt be sent to the CPU
- After the CPU receives the interrupt, it will clear IERx, set INTM to 1 and clear EALLOW, and then perform the interrupt service.
- PIEIFRx and PIEIERx to decode the interrupt vector table and determine the priority (as shown below)
1 is the highest, 8 is the lowest