A total of 4 registers are defined, the bit width is 32 bits, that is, the offset address*4
is the PS write data
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data ;
when 6 => PERIOD_LEN_REG <= wr_data;
1: I2S_RESET_REG --Address 0*4
i2s_reset <= I2S_RESET_REG(0); --Reserved
unused
tx_fifo_reset <= I2S_RESET_REG(1);
-->High effective
rx_fifo_reset <= I2S_RESET_REG(2);-->High effective reset
2 : I2S_CONTROL_REG -- address 1*4
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
3: I2S_CLK_CONTROL_REG --- address 2*4
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG (7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
4:PERIOD_LEN_REG ---- address 6*4
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0))) ;
receive the size of the fifo
以下是PS读数据
when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));---》地址10*4
when 10 -- "the high 24 bits are the data received by sampling - "the low 8 bits are the value of the frequency division counter