Introduction to DMA (Direct Memory Access)

What is DMA (Direct Memory Access)

  • DMA bypasses the CPU, opening a "tunnel" between memory and peripherals , directly controlling the operations between memory and peripherals, and is completely controlled by hardware.
  • In this way, the data transmission does not pass through the cpu , and a series of operations such as protection and recovery of the CPU scene are not required, thereby reducing the overhead .

how to run

  • Ask the cpu for the system bus : accept the DMA request from the peripheral and send a bus request to the CPU. The CPU responds to the bus request, issues a bus response signal, takes over the bus control, and enters the DMA operation cycle.
  • On the system bus, carry out data transmission between memory and peripherals : determine the address and length of the main memory unit for transmitting data, and can automatically modify the main memory address count and transfer length count. Specifies the direction of data transfer between the main memory and peripherals, sends out read and write control signals, and executes data transfer operations.
  • Return Bus : Sends the CPU the end of the DMA operation.

How to transfer

  • There is a data path between the main memory and the DMA controller. When the two access the data path at the same time, conflicts may occur. There are the following solutions:

Stop CPU access to main memory (CPU basically does not work, DMA has the final say)

  • Brief analysis: DMA requires the use of the bus, and the CPU gives it to DMA.
  • The DMA interface sends a signal to the CPU, asking the CPU to relinquish control of the related lines (address lines, data lines, and related control lines).
  • After the DMA interface obtains the bus control, it starts data transfer.
  • After the data transfer is over, the DMA interface informs the CPU that the main memory can be used and returns the bus control to the CPU.
  • During this transmission process, the CPU is basically in a non-working state and maintains the original state.

DMA and CPU access memory alternately (CPU work time-sharing, CPU has the final say)

  • Brief analysis: The CPU work is divided into two cycles: the cycle of accessing the main memory and the cycle of not accessing the main memory. The former CPU accesses the main memory, and the latter DMA accesses the main memory.

  • This method is suitable for the case where the CPU's working cycle is longer than the main memory access cycle. For example, if the working cycle of the CPU is 1.2us, and the access cycle of the main memory is less than 0.6us, one CPU cycle can be divided into two cycles, C1 and C2. Among them, C1 is dedicated to DMA access, and C2 is dedicated to CPU access.
  • This method does not require the process of application, establishment and return of the bus usage right, and the bus usage right is controlled by time-sharing through C1 and C2.

Periodic appropriation (negotiable with each other, no interruption is allowed)

  • Brief analysis: CPU and DMA negotiate with each other, DMA is used when CPU does not need to access memory; DMA cannot be interrupted when CPU accesses memory; when both access memory at the same time, DMA accesses memory.
  • This method is a compromise between the first two methods. When the I/O device does not have a DMA request, the CPU accesses the main memory as required by the program. Once the I/O device has a DMA request, three situations will be encountered.
  • The first is that the CPU is not accessing memory at this time (for example, the CPU is executing the multiplication instruction), so the I/O memory access request does not conflict with the CPU;
  • The second type is that the CPU is accessing memory, and the CPU must wait for the end of the access cycle before giving up the bus ownership.
  • The third is that the I/O and the CPU request memory access at the same time, and a memory access conflict occurs. At this time, the CPU must temporarily give up the bus occupancy, and the I/O device will use one or several access cycles.

For reference, see for more details: blog

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