Why is there memory paging
At present, our small kernel is still working under the segmentation mechanism, because there is only one loader running in memory, so there will be no problem of insufficient memory. If the paging function is not turned on at this time, and the physical memory space is insufficient, as shown below
At this point, process C wants to execute, but the memory space is insufficient. Either wait for process A or process B to complete execution, so that there is a continuous memory space. Either change the A3 segment of process A or the B1 segment of process B to the hard disk to free up some space, which can also accommodate the execution of process C.
Waiting is an extremely bad user experience, so you can only replace the segment to the hard disk, but the size of the segment is not fixed. If the segment is too large, then there are too many IO operations, and the response speed of the machine will be very slow.
The essence of this situation is that under the segmentation mechanism, linear addresses are equivalent to physical addresses. So even if there is 10M of free space under process B, because the two pieces of free space are not continuous, process C cannot use the 10M of free space under process B.
According to this idea, this problem can be solved only by mapping the linear address to any physical address through a certain mapping relationship. To achieve the continuity of linear addresses, and physical addresses do not need to be continuous, so the paging mechanism was born.
primary page table
The paging mechanism works under the segmentation mechanism. In protected mode, the segment base address is found through the selector, and the segment base address: the offset within the segment is combined into a linear address. After the linear address is obtained, the page will be opened according to whether the To find the actual physical address, use a picture to explain more clearly
The paging mechanism works in two ways:
1. Converting linear addresses to physical addresses
2. Replacing unequal-sized segments with equal-sized pages
as the picture shows:
The linear address that needs to be mapped through the paging mechanism has a tall name, the virtual address
Suppose we map byte by byte
Then 4GB page table entries will be stored in the page table, and the size of the page table = 4GB*4=16GB, which is obviously unreasonable, and a page cannot only occupy 1B
We need to balance the relationship between the size of the page and the number of pages, because page size * number of pages = 4GB, if you want to reduce the size of the page table, you can only increase the size of one page. Finally, the limit is determined through mathematics, and 4KB is set as the optimal page size
In this case, 4GB of memory is divided into 1MB memory blocks, each memory block is 4KB in size,
The mapping relationship between page table and memory is shown in the figure
With the page table, how to convert linear addresses to physical addresses?
Under the first-level page table, the upper 20 bits of the linear address are used as the index of the page table entry, which is similar to the index of the array. The physical address of the corresponding page is found in the page table through the index, and then the physical address + the lower 12 bits of the linear address form the real physical address. The process is shown in the figure
secondary page table
No matter how many levels of page tables, the standard page size is 4KB, which will not change. So a 4GB linear address space has at most 1M standard pages. The first-level page table is to place the 1M standard pages into one page table, and the second-level page table is to place the 1M standard pages into 1K page tables on average, and each page table contains 1K page table entries. The page table entry is 4 bytes in size, so the size of the page table is also 4KB
Since the original page table is divided into 1K page tables, these page tables must be managed uniformly. To this end, there is a dedicated page directory table to store these page tables. The page table stored in the page directory table is called a page directory entry (PDE). The page directory entry is also 4KB, and there are at most 1K page directory entries, so the page directory table is also 4KB.
The model of the secondary page table is shown in the figure
Although the principles of the second-level page table and the first-level page table are the same, they are very different in structure, so the conversion method of virtual address to physical address has also changed a lot.
First, locate a page table in the page directory table through the upper 10 bits of the virtual address, that is, locate the directory entry.
Then find the location of the physical page in the previously located page table through the middle 10 bits of the virtual address
The remaining 12 bits of the last virtual address are used as the in-page offset of the found physical page
The address translation process is shown in the figure
Structure of PDE and PTE
P bit: exists bit, when it is 1, it means that the page is in memory
RW: read and write bit, when it is 1, it can be read and written, and when it is 0, it is readable and not writable.
US: normal user/super user bit, when it is 1, it means it is in User level, that is, level 3 privilege level
PWT: page-level write-through bit, if it is 1, it means that this item adopts the write-through mode, which means that the page is not only ordinary memory, but also a cache
PCD: page-level cache prohibition bit, if it is 1, it means The page enables the cache
A: access bit, 1 indicates that the page has been accessed by the CPU
D: dirty page bit, when the CPU performs a write operation on a page, this is assigned 1
PAT: page attribute table bit, which can be used in page one Set the memory attribute G: global bit at the granularity of the
level, and a value of 1 means that the page is always saved in the cache TLB
Enable paging mechanism
Enabling the paging mechanism needs to complete the following three steps
: 1. Prepare the page directory table and page table
2. Write the page table address into the control register Cr3
3. Set the PG bit of the register Cr0 to 1
Create page directory table and page table
----------创建页目录及页表----------
setup_page:
mov ecx, 4096
mov esi, 0
.clear_page_dir:
mov byte [PAGE_DIR_TABLE_POS + esi], 0
inc esi
loop .clear_page_dir
.create_pde:
mov eax, PAGE_DIR_TABLE_POS
add eax, 0x1000 ; 此时eax为第一个页表的位置及属性
mov ebx, eax ; 此处为ebx赋值，是为.create_pte做准备，ebx为基址。
; 下面将页目录项0和0xc00都存为第一个页表的地址，
; 一个页表可表示4MB内存,这样0xc03fffff以下的地址和0x003fffff以下的地址都指向相同的页表，
; 这是为将地址映射为内核地址做准备
or eax, PG_US_U | PG_RW_W | PG_P ; 页目录项的属性RW和P位为1,US为1,表示用户属性,所有特权级别都可以访问.
mov [PAGE_DIR_TABLE_POS + 0x0], eax ; 第1个目录项,在页目录表中的第1个目录项写入第一个>页表的位置(0x101000)及属性(7)
mov [PAGE_DIR_TABLE_POS + 0xc00], eax ; 一个页表项占用4字节,0xc00表示第768个页表占用的目录项,0xc00以上的目录项用于内核空间,
; 也就是页表的0xc0000000~0xffffffff共计1G属于内核,0x0~0xbfffffff共计3G属于用户进程.
sub eax, 0x1000
mov [PAGE_DIR_TABLE_POS + 4092], eax ; 使最后一个目录项指向页目录表自己的地址
;下面创建页表项(PTE)
mov ecx, 256 ; 1M低端内存 / 每页大小4k = 256
mov esi, 0
mov edx, PG_US_U | PG_RW_W | PG_P ; 属性为7,US=1,RW=1,P=1
.create_pte:
mov [ebx+esi*4],edx ; 此时的ebx已经在上面通过eax赋值为0x101000,也就是第一个页表的地址
add edx,4096
inc esi
loop .create_pte
;创建内核其它页表的PDE
mov eax, PAGE_DIR_TABLE_POS
add eax, 0x2000 ; 此时eax为第二个页表的位置
or eax, PG_US_U | PG_RW_W | PG_P ; 页目录项的属性US,RW和P位都为1
mov ebx, PAGE_DIR_TABLE_POS
mov ecx, 254 ; 范围为第769~1022的所有目录项数量
mov esi, 769
.create_kernel_pde:
mov [ebx+esi*4], eax
inc esi
add eax, 0x1000
loop .create_kernel_pde
ret; 把页目录地址赋给cr3
mov eax, PAGE_DIR_TABLE_POS
mov cr3, eax
; 打开cr0的pg位(第31位)
mov eax, cr0
or eax, 0x80000000
mov cr0, eax