TSMC 2nm and 3nm process
Taiwan Semiconductor Manufacturing Co., Ltd., Chinese abbreviation: TSMC, English abbreviation: tsmc, is a semiconductor manufacturing company. Founded in 1987, it is the world's first professional integrated circuit manufacturing service (wafer foundry) enterprise. Its headquarters and main factory are located in Hsinchu Science Park, Taiwan Province of China.
In 2017, the field share was 56%. In the first quarter of 2018, consolidated revenue was US$8.5 billion, a year-on-year increase of 6%, net profit was US$3.0 billion, a year-on-year increase of 2.5%, gross profit margin was 50.3%, and net profit margin was 36.2%, of which 10nm wafer shipments accounted for 19% of total wafer revenue. As of April 19, 2018, the US stock TSM had a market value of $217.4 billion and a static price-earnings ratio of 19.
On the evening of August 3, 2018, TSMC reported that the computer system was attacked by a computer virus, causing the machine shutdown of the main factories such as Zhuke Wafer 12, Zhongke Wafer 15, and Nanke Wafer 14. . TSMC confirmed that it was attacked by a virus, but it was not rumored to be hacked. On August 4, TSMC informed the outside world that a solution had been found.
On August 26, 2020, Luo Zhenqiu, general manager of TSMC (Nanjing) Co., Ltd., said at the 2020 World Semiconductor Conference that TSMC's 5-nanometer products have entered the mass production stage, and 3-nanometer products will be available in 2021 and enter in 2022. Mass production.
On October 26, 2021, TSMC announced the launch of the N4P process technology.
TSMC 2nm, the problem is getting more and more serious
SMC's plan to build a brand new chip manufacturing plant in Taichung City on the island has led its lawmakers to demand two gas-fired power plants to manage the facility's electricity consumption. The facility is designed to produce semiconductors using an advanced 2-nanometer (nm) semiconductor process and is planned to be TSMC's second 2-nanometer manufacturing facility. The first plant will be built in Hsinchu, Taiwan, where the company has already obtained environmental approvals. Taichung City Councilor Mr. Lin Chi-Feng recently revealed the details of the planned factory in Taichung. Lin Chi-Feng said that the media reported that the daily water consumption of the Zhongke plant is about 49,000 tons. According to Taipower estimates, the new TSMC Nanke 3-nanometer plant consumes electricity for one year. The volume is about 7 billion kWh. If the newly expanded plant of TSMC Zhongke is a 2-nanometer process, the power consumption will be even more amazing than that of a 3-nanometer factory. After the expansion of TSMC's plant, the daily consumption of water and electricity is staggering, requiring the construction of medium-fire gas generating units as soon as possible. Zhang Fengyuan, director of economic development, said that the TSMC Zhongke plant uses about 100,000 tons of water a day, and uses up the power generation of one and a half units of the Zhonghuo coal-fired power plant. The energy consumption is staggering. TSMC's Zhongke plant uses about 100,000 tons of water a day, which can eat up the power generation of one and a half units of the Zhonghuo coal-fired power plant. It is hoped that TSMC will use more green power in the future, especially the green power of offshore wind power will be connected as soon as possible, and TSMC has already purchased a large amount of green power energy. If coal-fired power generation is not used, medium-fired gas-fired units should be built as soon as possible, especially experts and scholars estimate that the proportion of TSMC's electricity consumption in Taiwan will increase from 4% to 8% in 2025, which is equivalent to doubling the growth rate. In June, plans for TSMC's TSMC 2nm fab were reported, with the first 2nm fab to be built in the Hsinchu Technology Park, but the company may re-evaluate a second after facing water shortages earlier this year 2nm fab plans. TSMC's first factory capable of producing chips using its N2 manufacturing technology will be at a factory near Baoshan, Hsinchu County, in northern Taiwan. In 2021, the company established a new R1 R&D facility, which will be used for the N3 and N2 nodes. There have been no reports of TSMC's groundbreaking ceremony at the Hsinchu Science Park, but the company announced that the plant will be built in four phases.
In order to ensure a continuous water supply for its upcoming cutting-edge fab, TSMC is reportedly evaluating a site in the recently established Qiaotou Science and Technology Industrial Park near Kaohsiung in southern Taiwan, according to reports from Taiwanese media. In a statement sent to the media, TSMC reiterated its plans to build a second N2-enabled GigaFab (a fab with at least 100,000 wafer starts per month) near Taichung in central Taiwan, but acknowledged that it has not yet acquired the facility soil of. The company also added that it considered a number of factors before making its final decision. The main conclusion is that TSMC still plans to build two GigaFabs capable of processing wafers using its N2 fabrication technology.
TSMC talks about 2nm implementation
At the VLSI Technology and Circuits Symposium in June 2021, a short course on "Advanced Process and Device Technology for 2nm-CMOS and Emerging Memory" was held. In this article, the first two presentations on leading edge logic devices will be reviewed. The two presentations are complementary and provide an excellent overview of possible developments in logic technology.
TSMC: CMOS device technology for the next decade
Gate length (Lg) scaling of planar MOSFETs is limited to about 25 nm because of poor control of sub surface leakage by a single surface gate.
Adding more gates (such as in FinFETs), where the channel is confined between three gates, can scale Lg to about 2.5 times the channel thickness. FinFETs have evolved from Intel's original 22nm with highly sloped fin walls to today's more vertical walls and high mobility channel FinFETs implemented by TSMC for the 5nm process.
Taller fins increase the effective channel width (Weff), Weff = 2Fh + Fth, where Fh is the fin (Fin) height and Fth is the fin (Fin) thickness. Increasing Weff increases the drive current for heavily loaded circuits, but excessively high fins waste active power. Straight and thin fins favor short channel effects, but Fw is limited by reduced mobility and increased threshold voltage variability. Implementing a high-mobility channel in 5nm technology (the authors noted, SiGe for pFET fins) improved the drive current of the TSMC by about 18%.
As devices are scaled down, parasitic resistance and capacitance will become a new issue. CPP (Contacted Poly Pitch) determines the standard cell width (see Figure 1), which is composed of Lg, Contact Width (Contact Width: Wc) and Spacer Thickness (Spacer Thickness: Tsp), CPP = Lg + Wc + 2Tsp. Reducing Wc increases parasitic resistance unless process improvements are made to improve contact, and reducing tsp increases parasitic capacitance unless slower dielectric constant spacers are used.
Figure 1. Standard cell size.
As the standard cell height decreases, the number of fins per device must be reduced (fin reduction), see Figure 2.
Figure 2. Fin reduction.
Fin depopulation reduces cell size, increases logic density and provides higher speed and lower power, but it does reduce drive current.
Transitioning from FinFETs to stacked Horizontal Nanosheets (HNS) increases flexibility by changing sheet width (sheet width: see Figure 3) and the ability to increase Weff by stacking more sheets.
Figure 3. Flexible slice width.
Add sheets and add Weff, Wee = N*2(W+H), where N is the number of sheets, W is the width of the sheets, and H is the height (thickness) of the sheets. Ultimately, the number of sheets is limited by the performance of the bottom sheets. The spacing between sheets decreases as parasitic resistance and capacitance decrease, but must be large enough to allow gate metals and dielectrics to enter the gap. Below the HNS stack is a bottom parasitic mesa device that can be controlled by implantation or dielectric layers.
In FinFETs, nFET electron mobility is higher than pFET hole mobility. In HNS, the mobility is more unbalanced, with higher electron mobility and lower hole mobility. Hole mobility can be improved by cladding the channel with SiGe or using a Strain Relaxed Buffer, but both techniques increase process complexity.
Imec introduced a concept called Forksheet (FS), in which a dielectric layer is placed between the nFET and pFET, reducing the np pitch, resulting in a more compact standard cell, see Figure 4.
Figure 4. Forksheet
In addition to HNS with FS, there is also CFET (Complementary FET), which stacks nFET and pFET, thus eliminating the need for horizontal np spacing.
Figure 5. CFET.
CFET options include monolithic integration, where both nFET and pFET devices are fabricated on the same wafer. There is also sequential integration, in which nFETs and pFETs are fabricated on separate wafers and then combined, both options have multiple challenges still under investigation.
In addition to CFETs, the speaker also talked about 3D integration of transistors into Back End Of Line (BEOL) interconnects. These options require low-temperature transistors with polysilicon channels or oxide semiconductors, which present various performance and integration challenges.
In Front End Of Line (FEOL), options other than CFETs are being explored, such as high mobility materials, Tunnel FETs (TFETs), Negative Capacitance FETs (NCFETs), low temperature CMOS (Cryogenic FETs) CMOS) and low-dimensional materials.
Low-dimensional materials take the form of nanotubes or 2D materials that offer shorter Lg and lower power than HNS, but are still in the early stages of research. Low-dimensional materials are also suitable for the HNS/CFET approach, with the option of stacking many layers.
IMEC: HNS/FS/CFET Options
As FinFETs reach their limits, the fins are getting taller, thinner, and closer together. Reducing the number of fins is reducing drive current and increasing variability, see Figure 6.
Figure 6. FinFET scaling.
State-of-the-art technology today is a 6-track cell with 2 fins per device. The move to single fins and narrower np pitches will require new device architectures to improve performance, see Figure 7.
Figure 7. 6-Rail Cell
To continue CMOS scaling, a transition from FinFET sot HNS to HNS with FS and CFET is required, see Figure 8.
Figure 8. Nanosheet architecture for CMOS scaling.
Transitioning from FinFET to HNS offers several advantages, large Weff, improved short channel effect, which means shorter Lg and better design flexibility due to the ability to vary the chip width, see Figure 9.
Figure 9. From FinFET to HNS.
The speaker goes on to detail HNS processing and some challenges and possible solutions. Except for the four main blocks, the HNS process is very similar to the FinFET process, see Figure 10.
Figure 10. HNS process flow.
Although the HNS flow is similar to the FinFET flow, the different key blocks are difficult. Releasing the etch and achieving multiple threshold voltages is particularly difficult. There is a lot of good information on the details of the process module changes required for HNS, which is beyond the scope of a review article like this one. One thing not explicitly discussed is that in order to scale the HNS process to 5-rail cells, Buried Power Rails (BPR) is required, another difficult process module still in development.
As seen in the previous demonstration, FS can achieve further extensions of HNS. Figure 11 shows a more detailed view of how the dielectric walls shrink the HNS cell.
Figure 11. Horizontal Nanosheet/Forksheet architecture comparison.
The FS process requires the insertion of dielectric walls to reduce the np spacing, Figure 12 illustrates the process flow.
Figure 12. Forksheet process.
In addition to FS, CFETs provide zero horizontal np spacing through stacked devices. Figure 13. Illustrates the CFET concept.
Figure 13. CFET concept.
CFETs are especially interesting for SRAM scaling. SRAM scaling has slowed and cannot keep up with logic scaling. CFETs offer the potential to restore SRAM scaling to historical trends, see Figure 14.
Figure 14. SRAM scaling using CFETs.
As mentioned earlier, there are two CFET fabrication methods, monolithic and sequential. Figure 15 compares the advantages and disadvantages of the two approaches.
Figure 15. CFET fabrication options.
On December 27, 2021, Wei Zhejia, President of TSMC, said that TSMC has actively expanded its factories in Hsinchu, Tainan, and Kaohsiung in recent years. In order to consider the balance of production capacity and the dispersion of risks, Taichung must be one of the options for factory expansion.
TSMC expects to expand the 2nm plant in Baoshan, Bamboo Branch. If there is insufficient land in Bamboo Branch, TSMC may go to Taichung to expand 2nm production capacity.
Taichung's excellent conditions and advantages make high-tech industry talents willing to stay in Taichung, and Taichung is also one of the options expected to expand the factory.
TSMC's 2nm process technology will be mass-produced in 2025. According to TSMC's plan, a 2nm plant will be set up on the Baoshan land in Hsinchu Science Park. At present, the Bamboo Branch Administration is in the process of obtaining relevant land. However, if the bamboo branch land is insufficient, TSMC may go to Taichung to expand the 2nm production capacity.
TSMC recently decided to build a factory in Kaohsiung to produce 7nm and 28nm process chips. Nanke is the production center of 5nm and 3nm advanced processes. In order to balance the layout of the northern, central and southern regions, Taichung will be the focus of TSMC's future expansion of advanced process capacity. one.
Regarding the plant expansion plan, TSMC maintains a consistent attitude, claiming that it does not rule out any possibility. There are many considerations for the location of the plant, and it will actively cooperate with the authority to evaluate Hsinchu, Taichung, and Kaohsiung and other suitable sites for semiconductor construction.
As for the water used in the technology industry, the relevant personnel in Taichung City pointed out that there are many enterprises in Taichung City that have reclaimed water, including TSMC, AUO, Zhonglong, etc., and they have negotiated to obtain 100,000 tons of reclaimed water every day to ensure that water is safe and free of water. Reuse.
According to Taiwanese media DigiTimes and TechTaiwan, TSMC has started trial production of 3nm process (called N3) chips at Fab 18 in the South Taiwan Science Park near Tainan. Chip HVM using the new node will start in the second half of 2022, but due to the cycle time of the new process exceeding 100 days, the first N3 chips made by TSMC will ship in early 2023. The first Apple devices with 3nm chips are expected to debut in 2023, including the iPhone 15/Pro series models with A17 chips and Apple's Silicon Mac computers with M3 chips (all names are tentative).
TSMC's N3 manufacturing technology is a next-generation node for foundries designed for smartphone and high-performance computing (HPC) applications, a departure from TSMC's strategy of typically addressing mobile designs first. The new process will actively use "over 20 layers" of extreme ultraviolet lithography (EUV), a substantial improvement over the existing N5 base node. TSMC promises 10% to 15% better performance (at the same power and transistor count), up to 30% lower power consumption (at the same clock and complexity), up to 70% higher logic density and 20% higher SRAM density promote.
TSMC Nanke's new 3-nanometer factory officially opened this summer. According to the latest law, the news will be disclosed. N3 is expected to be mass-produced in the second half of 2022. Compared with 5-nanometer (N5), more new product designs will be finalized in the first year (Tape -out), will see significant revenue contribution in the first quarter of 2023; at the same time, N3E will be launched to extend the N3, and the initial estimate of the mass production schedule will be one year after the N3 mass production (the second half of 2023).
TSMC plans to have a production capacity target of 50,000 to 60,000 units per month for 3nm, with 30,000 to 40,000 units in place in March 2023, and Apple will take the lead, and it is scheduled to enter the trial from December 2022 to January next year. production, mainly targeting new machines in 2022. The first wave of customers also includes Intel. In 2023, a new generation of products will be introduced into TSMC's 3nm and 4nm processes.
Intel will hold a semiconductor supplier summit in mid-December 2022, and company executives also plan to meet with TSMC. The industry pointed out that Intel not only delayed the process, but also the market is being pushed by its competitors step by step. Therefore, the competitiveness of next-generation products is very important, and it must rely on external resources to help regain market share. Although Intel has made it clear that the U.S. government does not want to subsidize foreign manufacturers, it still has to soften its stance under commercial considerations in order to obtain enough 3nm production capacity.
TSMC will point out that 5G mobile phone chips and HPC computing chips will be the main products in the first year of 3-nanometer mass production. In addition to Apple and Intel being listed in the first wave of N3 cooperation, MediaTek, AMD, Qualcomm, Nvidia, etc. are also planning to follow keep up. The industry is optimistic that TSMC's 3-nanometer is the most competitive process for the next generation. In addition, the demand for processes above 3-nanometer will remain high.
Reference link
https://mp.weixin.qq.com/s/pfMhmskEtabtqNXoRm_2tQ
https://mp.weixin.qq.com/s/a_67sNfHlVo-MSlAS3t-rA
https://mp.weixin.qq.com/s/ EOgtkOpyTgqB3GV0GwYGqA