Timingdesigner timing designer introductory basic tutorial
Timingdesigner is a flexible and powerful software for drawing timing diagrams. It has certain application value in the development of fpga or dsp. This post introduces the basic operations of timingdesigner, including drawing of clocks, signals, and buses. Please indicate the original for reprinting: http://blog.csdn.net/u013608300/article/details/78988523
1. Installation
The installation process is abbreviated. Baidu is a bunch. The version used in this tutorial is V9.103. Figure 1 shows the interface when the software is opened. This time we will introduce adding signals, buses, clocks, and frequency division clocks (add signal. add bus. add clock. add derived). clock) operation. (Derived clock, understood as a derivative clock below, for the convenience of me calling her a divided clock, please correct me for the specific name)
figure 1
2. Add a clock
Timing is inseparable from the clock. Before adding a signal, let's take a look at the most intuitive operation of adding a clock. Click Figure 2 add clock. The pop-up interface is shown in Figure 3
figure 2
Figure 3 is the dialog box that pops up when adding clock. The name of the clock is Clk_50M, and the direction is input. Below 3 can set the frequency of the signal, 4 can set the duty cycle and clock jitter, and the jitter time is 0. 5 It is very convenient to configure other parameters, so you can explore it yourself. The waveform after clicking ok is shown in Figure 4.
image 3
Figure 4 is the added clock. When operating a clock or signal, generally select the arrow of 1 first, and you can perform operations such as 2 pairs of waveform enlargement (the shortcut key for enlargement and reduction is +-), and the reduced waveform is shown in Figure 4 In the second part, double-click 1 in the second part of Figure 4, and Figure 3 can pop up again to edit the clock again.
Figure 4
3. Frequency division clock
After adding the play clock, we will add the divided clock, (add deirved clock is called the divided clock is a bit far-fetched, please point out the appropriate name), stand-alone add derived clock, pop up Figure 5. This time I got a 100M clock, named Clk_100M, this clock is an internal clock, 3 is the reference clock for setting this clock, which is the Clk_50M clock we set in 2, 50M/0.5, we get a 100M clock, The delay is set to 0, and the effect of clicking ok is shown in Figure 6.
Figure 5
In Figure 6, we can see the relationship between the two clocks being 2 times the frequency.
Figure 6
4. Add signal
Add and click add signal, and the dialog box shown in Figure 7 pops up. Here I named the signal Rst_n (reset signal, low-level reset), the port direction is input, and the initial level is high
Figure 7
Figure 8 is the confirmed interface. When we stand alone at the place pointed by the arrow, the effect is shown in Figure 8. We can drag the rising edge in this box to adjust its time position. Click behind Rst_n a few more times to try. The effect is shown in Figure 8.
Figure 8
5. Add a bus
Click add bus, as shown in Figure 9. The bus is named data_in, and the direction is input. The initial value is 0 (decimal). After clicking ok, see Figure 10.
Picture 9
At this time, there is no bus waveform in Figure 10, click on the arrow, as shown in Figure 10. The data_in in Figure 10 is not continuous, first select the discontinuity, and then click 2 in Figure 10, see the effect for yourself
Picture 10
Select Figure 11, then double-click to set its value, and the Figure 12 dialog box will pop up
Picture 11
Set the value of data_in (decimal) in Figure 12
Picture 12
The final effect is shown in Figure 13
Figure 13
The basic operation introduction is over, let's explore and learn other content together.
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Timingdesigner timing designer introductory basic tutorial