Introduction: This article will take mainstream learning chips as an example to sort out the startup process of the following typical embedded Linux devices. Currently, the more popular learning chips are S5PV210, S3C2440, AM335x, IMX6ULL, STM32MP157.

0, basic concepts

BL0 : The code built into the iROM of the SOC is the code burned by the chip manufacturer in advance. This part of the code will determine which device to boot from according to the specified pin level. BL0 is the copy function of Nand Flash, NorFlash, iNand and other devices (because you want to read Flash, you need to initialize the following Flash simply). His main job is to copy BL1 from Flash to iRAM or NorFlash to run. (BL0 is set before the SOC leaves the factory, and the chip manufacturer does not know what kind of DRAM will be connected to the board in the future, so the configuration and initialization of the memory and Flash are left to BL1)

BL1 : It is the code written by the developer, which can be a bare-metal program written by yourself, or uboot or others. BL0 only does partial initialization of the memory, and BL1 needs to turn off the watchdog, set the clock, and set the abnormal interrupt vector table.

iRAM : Internal SRAM chip built-in memory, you can run programs directly.

SOC : System on Chip system level chip, the chip integrates cpu, memory, Flash and other controllers, cache, etc.

Note : When the system is just powered on, neither the memory nor Flash is initialized and cannot be used. Only iRAM (usually a dozen K) can be used, and the real code is in Flash, and Flash (except Nor) cannot run programs directly. Hardware related introduction reference: ARM embedded hardware introduction

1、S3C2440

Introduce
a 32-bit CMOS microcontroller based on ARM920T core developed by Samsung S3C2440, the main frequency is up to 400MHZ, the structure is relatively simple, and the overall performance is worse than S3C6410. No iROM, 4K iRAM.
The S3C2440 memory address table

is shown in the figure. When the NandFlash is connected and the OM pin is set to Nand to start, because the program cannot run the program on the nand, the 0 address of the on-chip 4K memory (iRAM) is the 0 address of the entire memory; When NorFlash is connected and the OM pin is set to Nor start, the 0 address of NorFlash is the 0 address of the memory, and the on-chip RAM base address is 0x4000_0000.
After S3C2440 is powered on, it starts to run from address 0. If it is started from nand, it starts to run from iRAM. If it starts from Nor, it starts to run from NorFlash.
Start the process when the Nand Flash is externally connected.
At this time, the base address of the iRAM (on-chip memory) is the memory 0 address.
Step 1: After Reset, the Nand Flash controller will copy the 4K code before Nand to stepping stone to run.
Step 2: This part of the code is responsible for configuring the memory and Flash, then copy the uboot code into the memory, and then jump to the memory to run.
Step 3: Finally uboot starts the Linux kernel (OS), then the kernel mounts the root file system and enters the command line to start the application.
Start the process when the Nor Flash is connected externally.
At this time, the address 0 of NorFlash is the address 0 of the memory.
Step 1: After Reset, the program runs directly from NorFlash, initializes the memory, and copies uboot to the memory.
Step 2: Jumps to the memory to run, and then starts the kernel.

Supplement: NorFlash participates in the unified memory addressing, that is, the pointer points to the NorFlash memory address to directly operate Nor, and nand does not participate, and the nand controller needs to be operated to read and write nand.

2、S3C6410

Introduction
S3C6410 is an application-level SOC based on the ARM11 architecture launched by Samsung. The main frequency is up to 667MHz.
IROM (0x0800 0000) 64M only uses 32K as BL0, 0 address is mapped to IROM
IRAM (0x0C00 0000) 64M, only 8K is used, load BL1, As steppingstone
Start-up process
Step 1: After Reset, read BL0 from iROM to execute, and BL0 copies BL1 to iRAM to run.
Step 2: BL1 initializes the configuration memory and Flash, and then copies BL2 (uboot main code) to the memory. Then jump to the memory to run (uboot will determine whether it is running in iRAM or memory, if it is iRAM, it jumps to the memory to run; if it is in memory, it jumps directly to the main code to run). You can refer to the S3C6410 startup process.
The third step: BL2 is responsible for starting the Linux kernel (OS), then the kernel mounts the root file system and enters the command line to start the application.

3、S5PV210

Introduction
S5PV210 is an application processor developed by Samsung for multimedia devices such as smartphones and tablet computers. It uses an ARM Cortex-A8 core, 32K L1 cache, 512K L2 cache, working frequency up to 1GHz, and supports 2D/3D. Graphics acceleration, supports full HD, multi-standard video encoding.
IROM (0XD000 0000), the size is 64KB, for address 0, it is the boot area, and the mapping method is used, the same as 6410;
IRAM(,0xD002 0000), the size is 96KB, load BL1+BL2, steppingstone;
Start-up process
Step 1: Run BL0 after the CPU is powered on, and BL0 will read the first part of the startup code (BL1, 16KB in size) from the corresponding external memory to iRAM to run.
Step 2: BL1 is responsible for initializing Flash, and then reading BL2 into iRAM (the remaining 80KB) to run
Step 3: BL2 is responsible for initializing the memory, reading the kernel (OS) into the memory, and then starting the kernel.
uboot startup process
Since uboot is generally much larger than 96K, uboot does not actually start according to the above process. After uboot is compiled, uboot-spl.bin (BL1) and uboot.bin will be generated. The startup steps are as follows:
Step 1: BL0 after power-on Start running, load uboot-spl.bin (BL1) into iRAM and run
Step 2: uboot-spl.bin directly initializes the memory and Flash, directly copies uboot.bin to the memory, and then jumps to the memory to run , Bypassing BL2.
Step 3: Run uboot.bin to start the kernel.
After S5PV210 starts
BL0 for the second time and loads BL1, it will calculate the checksum of BL1. If it fails, the startup will fail. For the second startup, BL1 will be read from the second device. If the verification still fails, it will start via the serial port. If it fails, boot via USB, if it still fails, the entire boot process fails. As long as one succeeds, BL1 is executed.

4. AM335x and IMX6ULL

Introduction
AM335X is a microprocessor based on ARM Cortex-A8 core launched by TI (Texas Instruments), the highest frequency can reach 600M/800M/1GHz, with NEON coprocessor, secondary cache, 24-bit LCD controller and touch screen The controller has a resolution of up to 2048*2048.
IMX6ULL is a microprocessor based on the ARM Cortex-A7 core launched by NXP (NXP) with a maximum frequency of 800MHz.
Boot process
1. The AM335x
  startup process is similar to S5PV210. It supports multiple device startups. The SOC will save a list of startup devices, and then read BL1 in the order of this list. If the read succeeds, execute BL1, and if it fails, go to the next startup device. If this is the last boot device, it enters an endless loop. BL1 is responsible for initializing Flash and memory, then running the main uboot code, and then starting the Linux kernel.
2. IMX6ULL The
  startup process of IMX6ULL is the same as AM335x. The first time it fails, it will judge whether it is the first mirror. If it is, set the SW pin, specify the next startup as the second startup device, and then reset and restart.

IMX6ULL startup process

4. Summary

The startup process of these chips is similar. After power on, run BL0, BL0 to start BL1, BL1 initializes memory and Flash, then copy the code to the memory, and then jump to the memory to run.

For details, please refer to the official data sheet: Chip Manual Download

Typical ARM embedded Linux device startup process-S3C2440, S5PV210, AM3352x

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