S3C2440 and S5PV210 entry of many enthusiasts arm embedded processor, a lot of online information. Today we'll talk S3C2440 and S5PV210 startup process on a blog I introduced in norflah uboot boot process (important! This is the foundation). Today, we talk on the nandflash uboot boot process.
A. Nandflash and norflash
Also, as you no doubt feel a doubt what is norflash? What is nandflash? What are the similarities and differences between them?
norflash my last blog post has been introduced (and then repeat it)
1.norflash
norflash: norfalsh is a nonvolatile memory (NORFlash data remains stored in the loss of supply), with NORFLASH SRAM interface, sufficient to address the address pins, you can easily read a byte of each of its internal (Note that reading can be written to the flash is not random, usually write NOR flash process is:! unblocked -> erase -> write data because the flash feature is only flipped from 1-0, you can not flip from 0 to. 1. the erasure process is to a certain sector in the flash write 0xFFFFFFF full, then the write data), code instructions can be run directly on norflash. (Important! After power norfalsh data can be read in the write operation can not be performed directly in front of me have said very clearly)
Multi few long-winded, for norflash, the arm on the power after the processor can directly read the inside data (NORFLASH with SRAM interface, sufficient to address the address pins, it can be easily read its internal each byte), but! But pay attention! ! You can not write data directly! ! ! You can only see him as a <direct> SRAM (read only SRAM) read.
2.nandflash
nandflash: the internal nonlinear model macrocell provides an inexpensive and effective solution to achieve a large capacity solid state memory. Nand-flash memory having a large capacity, rewritable speed, etc, suitable for mass storage of data. However NANDFlash the I / O interface and not a random access external address bus, it must be read in blocks of ways.
To summarize: norflash with an SRAM interface, sufficient to address the address pins, it can easily be <reads> each byte therein.
nandflash the I / O interface, and not the random access external address bus, the address data on the random access not to SRAM.
(Find the activation process, more than the concept is enough! Nandflash specifically how to get data in, next blog I alone explain)
Two. S3C2440 processor startup process
My English is not very good, six did not before, that much is tears. Chip Chinese data sheet to see friends can Baidu
<S3C2440 full set of Chinese manual (Chapter 1-27) .PDF>, translate quite well! Like this one! !
(Ratio S3C6410 Chinese translation manual data well too, S3C6410 Chinese data simply can not see)
I picked from Samsung S3C2440 Datasheet a processor chip memory map, as shown below:
As can be seen from the figure OM [1: 0] in the choice of different values, different address mapping relationship.
When OM [1: 0] 01 or 10 is selected in SROM (nGCS0) must be external norflash. After the processor power of the first instruction is fetched from 0x00000000, the SP ARM processor (provided to the stack pointer register at 0x40000FFF). Clock and complete DDR and other initialization and BootSRAM built in norflash running environment.
(Startup process and start the process of my previous article on the same)
When OM [1: 0] to select 00, the front of 4KB S3C2440 program built in the SRAM buffer nandflash will automatically copied to the BootSRAM. After that, the processor then begins program execution at 0x00000000.
(On the data sheet is written so! But !!)
Now the question again:
What 1. S3C2440 built-in SRAM buffers in the end is?
2. Why is it necessary to have a built-in SRAM buffer in order to start the program from nandflash in?
Each with a development board, when people tell you to DIP switch to the 01 or 10 states starting from norflash, the DIP switch to the 00 state start from nandflash. (But you thought that the above problem?)
What 1.S3C2440 built-in SRAM buffers in the end is?
S3C2440 block diagram of the built-in SRAM buffer as shown below:
S3C2440A boot code may be executed on an external NAND Flash memory. In order to support NAND Flash of BootLoader, S3C2440A equipped with a built-in SRAM buffers, called "Steppingstone". When booting, 4K-byte start NAND Flash memory will be loaded into and executed Steppingstone loaded into the boot code Steppingstone.
Usually boot code will copy the contents of NAND Flash to the SDRAM. By using hardware ECC, effectively check the NAND Flash data. On the basis of the copy is completed, the main program will be executed in the SDRAM.
When reset, the NAND Flash controller status pin (NCON (advanced flash memory), GPG13 (page size), GPG14 (address period), GPG15 (bus width) - see Pin Configuration) to acquire the connection of NAND Flash information, after power down or system reset, NAND Flash controller automatically loaded BootLoader 4K bytes of code. After the code is loaded in BootLoader, Steppingstone in BootLoader code has been executed.
(When during automatic boot, ECC will not go testing, so, NAND Flash is beginning 4KB should not contain bits related errors.)
I read the data from the data sheet of the removal of a large section of the above (maybe thinking you might still not very clear)
Let me summarize: For the interface norflash with the sram, after power processor can read from the instruction to be executed at 0x00000000. However, the processor is powered replaced nandflash not read directly from inside the command (address nandflash no map on the processor address space, only to be read by nandflash controller). S3C2440 solution is: a built-in SRAM buffer (Steppingstone), SRAM buffer automatically go to the front of 4KB of data to be copied to nandflash chip built BootSram (note !! chip design, internal hardware after power achieve, and I mentioned later bootrom unrelated). Thereafter, the processor fetches the instruction from BootSram.
2. Why is it necessary to have a built-in SRAM buffer in order to start the program from nandflash in?
Therefore, when the OM [1: 0] to select 00, S3C2440 internal procedures enabled the SRAM buffer will be in front of 4KB nandflash automatically copied to the BootSRAM. Thereafter, the processor starts executing the program (BootSRAM start address) at 0x00000000.
When OM [1: 0] 01 or 10 is selected in SROM (nGCS0) must be external norflash. After power is removed from the processor of the first instruction 0x00000000 (NORFlash can directly read the inside data there is no need to use SRAM buffer).
Here I would like to say a few words!
For S3C2440 processor M [1: 0] to select 01 or 10: norflash base address 0x00000000, SRAM top address 0x40000FFF. After power processor fetches the instruction from 0x00000000, arm processor SP (stack pointer register) points 0x40000FFF.
OM [1: 0] to select 00, S3C2440 internal procedures enabled the SRAM buffer will be in front of 4KB nandflash automatically copied to the BootSRAM. BootSRAM base address 0x00000000, the top 0x00000FFF. After power, arm processor fetches the first instruction from 0x00000000, arm processor SP (stack pointer register) points 0x00000FFF.
Eventually, all need to be mirrored uboot conveyed to the top of the SDRAM to run. For norflash can directly read transfer
Process is similar:
int i;
volatile char * norflash_base_addr = 0x000000000;
volatile char * ddr_base_addr = 0x300000000;
for (i = 0 ; i < length ; i++)
{
*(ddr_base_addr + i) = *(norflash_base_addr + i);
}
uboot inside the handling process As written above, except that it is written in assembler.
However, nandflash doing so can it?
Absolutely it is not possible (nandflash simply not connected to the address bus and the arm, the arm processors are they not had access to the address, only to access via nandflash controller), so to start from nandflash, in doing uboot transplant, need to write a function nandflash read. Nandflash controller to control the image to nandflash the uboot conveyed to the ddr. A power SRAM buffer 4KB in size nandflash automatically transported to the data in BootSRAM (done in hardware). Thereafter, when the mirror needs to be transported from uboot nandflash to the ddr, you can achieve (code completion) in code when porting. (Clear rationale thinking, because twice handling and implementation)
Do you understand it? Like I said before nothing to do, start to understand processes and processor architecture processor, main memory is to understand the various features and read the datasheet.
(Important! Startup code processor exceptions such as setting arm close to the scale watchdog Off On I / D cache and processor architecture such as this is closely related to the back of the blog I will analyze a section of)
