Computer controller and its design and implementation

Controller and its design and implementation

The function and structure of the central processing unit CPU

Functions of the central processing unit:

• A program is an ordered collection of instructions, and the process of program operation is essentially指从程序首地址开始，连续自动的处理指令序列，直到程序最后一条指令
• From the perspective of stored programs, the function of the central processing unit is实现连续自动的处理存储于主存储器的指令序列
• The instructions in the program are only used by the computer to transmit and calculate data or indicate the address of the next instruction

The tasks of the central processing unit

• Any instruction processing can be divided into two stages: fetching instructions and executing instructions. Program operation is to continuously fetch instructions and execute instructions cyclically until the end
• Fetch 2 tasks:
  • 1. Fetch the instruction code currently to be processed from the main memory to the register of the CPU
  • 2. Sequentially form the position of the next instruction to be processed on the memory
• Three tasks of executing instructions:
  • 1. Analyze instruction functions and addressing characteristics:
    • The instruction uses binary to represent its functional characteristics and the formation method of the operand storage location
  • 2. Generate a control signal sequence:
    • On the basis of analyzing the instruction operation code and address code, the controller generates and sends out a control signal sequence, analyzes the operation code of this instruction, identifies the functional characteristics of the instruction, and analyzes the addressing characteristics of the address code to identify the instruction to obtain the source operand and the destination operation Physical location
    • The effective address of the operand can be the main memory storage unit address, CPU register number, I/O device port address
    • The effective address of the transfer target can only be the address of the main memory storage unit
  • 3. Execution of the function and addressing characteristics of the instruction

Five tasks of the CPU

• Command control:CPU的首要任务。按程序规定的顺序处理指令，并自动从主存储器中取到CPU的寄存器中
• Operation control: According to the instruction code fetched from the main memory, a group of control signals are generated, and different control signals are sent to the corresponding components to control them to operate according to the function and addressing characteristics of the instruction
• Time control: There are strict time requirements in the two phases of fetching and executing instructions
• Data processing: perform arithmetic and logical operations on data and test program running status
• Interrupt request processing: Controlling interrupt request processing is an important task of the CPU

The structure model of the central processing unit

CPU registers

• The configuration of CPU commonly used registers:
  • General register GR: generally used to store raw data and calculation results
  • Accumulator AC: Accumulation register. Usually used to store the result information of ALU operations.
  • Instruction register IR: used to temporarily store the code currently being processed
  • Data buffer register MDR: used to temporarily store information exchange between the CPU and the main memory or IO device currently being transmitted指令字或数据字
    • Instruction word: unidirectionally read from the CPU from the main storage
    • Data word: Two-way read by CPU from main memory or IO device, and write by CPU to main memory or IO device.
    • Two functions of MDR:
      • Route transfer: data buffering for one-to-many or many-to-one route selection through MDR
      • Speed ​​compensation: CPU and main memory or IO device have speed difference in information transmission. Through MDR, CPU and main memory or IO device can independently transmit information to avoid waiting for each other.
  • Address buffer register MAR: used to temporarily store the instruction word or data word currently being transmitted when the CPU exchanges information with the main storage unit or IO device单元地址或端口地址
  • Program status register PSWR: temporarily store the status word of the currently running program

The main performance indicators of the CPU

• Word length: refers to the number of bits of binary data that the arithmetic unit can process at the same time
• Main frequency: CPU operating frequency
• On-chip Cache capacity: plays an important role in improving CPU speed
• The width of the address bus: The number of CPU address pin lines determines the maximum physical address space that the CPU can access
• The width of the data bus: The number of lines of the Cpu data pin, which determines the number of bits of the binary number that the CPU exchanges with the outside.

The function and structure of the controller

• Functional tasks of the controller
  • Command flow control
    • Instruction read control: read instruction codes from the main memory to the registers of the CPU
    • Instruction address formation: automatically form the address of the next instruction in the main memory
  • Instruction execution control
    • Command function recognition
    • Address calculation formation
    • Pointer read control
    • Data reading control
    • Data storage control
    • Data processing control
  • Interrupt handling control
    • Interrupt request selection
    • Program pause control
    • Program transfer control

  1. Instruction reading, pointer reading, data reading, data saving, data processing, program pause, and program transfer are controlled by the controller 控制型任务. Controlling tasks only require the control unit to generate control signal sequences. 2. Instruction address formation, instruction function recognition , Address calculation formation, interrupt request selection is the controller, 工作性任务which is executed by the controller itself

The structure of the controller

• Instruction preprocessing component
  • Program counter PC
  • Instruction decoder ID: separate operation code and address code
  • Address formation logic
• Timing signal generator: Generally, the response method is used to specify the processing time of each instruction to achieve the asynchronous connection of the sequence, so a timing signal is required to specify the execution time
• Control signal sequence generator: generate control signal sequences that meet different functional requirements
• Interrupt control logic: queuing selection for abnormal conditions, generating interrupt request signals and sending them to the control signal sequence generator

The realization method of control signal sequence generator

• Hard step line control
• Microprogram controller
• Gate array controller

Data path micro-operations and micro-commands for instruction processing

Instruction processing flow and status change

• The general flow of instruction processing:
  • Instruction fetch
    • Instruction read
    • Instruction address formation
  • Execute instructions
    • Command function recognition
    • Address calculation formation
    • Pointer read
    • Data read
    • Function implementation
    • Data saving
• Four judgments are made after the address calculation is formed:
  • 1. Indirect addressing? No, transfer to the second judgment, if yes, transfer to pointer reading, continue with 1, until the end of the indirect address to get the operand address
  • 2. Does the source operand need external access? (Ie memory or IO) If not needed, go to 3, if you need to read data, go to 3
  • 3. Whether it is RS or SS type transmission command, if yes, go to 4, if not, go to 4 after the function is implemented
  • 4. Does the destination operand need external access? If not, the instruction processing ends, if necessary, transfer to the data to save, and end the instruction processing

Extension: In the instruction format and instruction function classification in Chapter 2:

• For the binary operation two address (the address code field in the instruction word includes two address codes OP+Ad1+Ad2, Ad1 is both the result operand address and the address of another source operand, and Ad2 is the source operand address) instruction, According to the different physical storage components stored in the source operand, the instruction format can be divided into three types:
• SS memory memory type: 2 source operands are all from the main memory, and 2 address codes indicate the storage unit of the memory
• RR register register type: 2 source operands are from general registers, 2 address codes indicate the numbers of general registers
• RS register memory type:...

Data path of instruction processing and its micro-operation

• Address coding: slave controller -> memory, IO
• Instruction code: memory -> controller
• Data encoding: memory, IO-> arithmetic unit or reverse
• Data path: When information is exchanged between functional components, a path for information transmission is formed as an information path

Command read: (address coding, command coding)

• Address data path:PC-MAR-ABUS-M
• Command data path:M-DBUS-MDR-IR-ID-CU

Pointer reading: (address coding, pointer coding)

• Address data path: IR-MAR-ABUS-M(first indirect addressing) or MDR-MAR-ABUS-M(indirect addressing again)
• Pointer data path: M-DBUS-MDRor M-DBUS-MDR-PC(indirect addressing transfer instruction)

Data reading: (address coding and data coding)

• Address data path: IR-MAR-ABUS-M(direct addressing, relative addressing, indexed addressing) or MDR-MAR-ABUS-M(indirect addressing)
• Data path: M-DBUS-MDR-AC(GR general-purpose register) or M-DBUS-MDR(operation instruction with source operand in M)

Function implementation

• Arithmetic instruction realizes internal transmission of arithmetic unit
  • The data data path is: AC（GR/IR(Ad)）-ALUX-ALU-JPCL-AC(GR){RR指令}either AC（GR/IR(Ad)）-ALUX-ALU-JPCL-MDR{RS指令}or MDR-ALUX-ALU-JPCL-AC(GR){SR指令}orMDR-ALUX-ALU-JPCL-MDR{SS指令}
• RR transmission type instruction realizes the internal transmission of the arithmetic unit or the controller to the arithmetic unit
• Transfer instructions to realize the internal transmission of the controller

Data saving

• Address data path and data read status are the same
• Data data path: JPCL-MDR-DBUS-M(the destination operand is in the M operation instruction) or AC(GR)-MDR-DBUS-M(RS transfer instruction)

Micro commands and their relationship with micro operations

Micro-operation concept:

• Concept: It is an indivisible component or device action controlled or implemented by the CPU in the instruction processing flow
• Micro operation is the action of a component or device. Due to the different characteristics of the device and component, some components or devices need the control signal of the control signal sequencer to be realized. Therefore, the micro operation is divided into hard micro operation and soft micro operation.
• Hard micro operation: has nothing to do with the function of the control signal sequencer
• Soft micro operation
• According to the operating efficiency, micro-operations can also be divided into transmission and processing
• Transportability: used to create a data path
• Processability: Acting on prescribed information processing methods

Soft micro-operation

• The control generated by the control signal sequencer realizes the micro-operation控制信号称为微命令

  • Micro command is the smallest unit in the control signal sequence. One micro operation corresponds to one or more micro commands

• For processing micro-operations:

  • Hard micro operation: ID decoding, timing signal generation, control signal sequence generation
  • Soft and micro operation: PC+△, ALU operation is diverse (± and OR, etc.)

• For transitive micro operations:

  • Hard micro-operation: information transfer within the component, IR->ID (internal controller), ALU->JPCL (internal transmission of the arithmetic unit)
  • Soft and micro operation: the rest, IR->AC (calculator and controller)

• Control parts, execution parts

  • Control component: controller
  • Execution components: arithmetic unit, memory, IO

• The control part and the executive part realize two kinds of function relations, forward and reverse through the control line

  • Positive action: The control component sends various control signals, namely micro-commands, to the execution component through the control line, and the execution component generates actions that are micro-operations after receiving the micro-command
  • Reverse effect: the execution part sends the result status to the control part through the control line

1 example

• If a certain CPU structure is shown in 6-10, give the control signal required by SHR I 31 (right shift, indirect addressing, address) instruction
  • This instruction contains 4 state operations: read instruction, read pointer, function implementation and save data
  • The control signals needed to read the instructions include transmission and processing. For transmission:, PCout、MARin、Read、MDRin、MDRout、IRinthe control signals for processing include:PC+1
  • The control signal needed to read the pointer only includes the transmission,IR（Add）out、MARin、Read、MDRin
  • The control signal required for the function implementation only includes the processing, namelySHR
  • The control signal needed to save the data only includes the transmitted:MDRout、 MARin、 ACout、 MDRPin 、MDRout

Time sequence signal system and its control realization

Instruction cycle and time division

• Instruction cycle: the total time required for the CPU to process instructions

• 

• Machine cycle (CPU cycle, state cycle): In the instruction flow, the state maintenance time or the time interval between two state transitions

An instruction cycle is often represented by several machine cycles

• The instruction processing flow includes five states:
  • 1. Read instructions
  • 2. Read the pointer
  • 3. Read the data
  • 4. Function implementation
  • 5. Save data
• The machine cycle includes five types:
  • 1. Fetching cycle
  • 2. Interdigital cycle
  • 3. Access cycle
  • 4. Implementation cycle (execution cycle)
  • 5. Deposit cycle

1. The work tasks of various machine cycles are specified by the corresponding state operations.
2. Interrupt control is also a state in the operation of the CPU. So from the perspective of the CPU, in addition to the five cycles, there is also an interrupt cycle, so the CPU has 6 Types of machine cycles
3. The operating speed of the CPU is much faster than that of the main memory. Most of the state operations of the instruction implementation cycle can be completed within one access cycle. Therefore, the access cycle is usually used to calibrate the length of the machine cycle

• At most how many machine cycles an instruction cycle consists of is not only related to the addressing mode of the operand, but also related to the number of indirect addresses and the machine cycle of the implementation cycle

Beats and clock cycles

• It is necessary to divide the time period of a machine cycle into several time periods, and each time period performs a micro operation or a group of parallel micro operations
• Beat: the time to perform a micro operation or a group of parallel micro operations

The clock cycle is the smallest unit of time in the computer.
Micro operations are atomic operations that cannot be divided in the instruction processing flow, and the beat is an atomic time period that cannot be divided in the instruction cycle. A beat uses several clock cycles to represent a
8086 CPU. The machine cycle is represented by four basic clock cycles T1-T4, and any waiting clock cycle TW can be inserted between T3-T4

• 

Block diagram representation of the instruction cycle (four instructions flow)

Logical structure based on single bus model machine

• Features of single bus model machine:
  • ALU/PC/GR and other components are connected through the chip bus inside the CPU
  • Connect CPU/M/IO devices and other components outside the CPU through the system bus
  • Multiple components and devices can receive data on the bus at the same time, but only one component can send data to the bus at a time
  • There are 32 micro commands
    • 21 transmission micro operations
    • 11 processing micro-operations

Controller timing control (CPU control)

• Timing control concept:
  • How many machine cycles are used in an instruction cycle to execute the state operation sequence, how many beats are used in a machine cycle to execute the micro operation sequence, and how many clock cycles are used in one or a group of micro operations to execute
  • It refers to the control method of time calibration and sequence connection of different machine cycle micro-operation sequence execution
• Three ways
  • 同步控制（集中控制中央控制）
    • Concept; any micro operation and state operation are controlled by a unified timing (fixed timing control)
    • Three implementation schemes
      • Fixed-length machine cycle: the number of beats contained in various machine cycles is fixed
      • Extend machine cycle of indefinite cycle
      • Scattered beats and variable machine cycles
    • Advantages and disadvantages: simple and easy to control, but low efficiency
  • 异步控制：（分散控制局部控制）
    • Concept: Micro-operations and state operations do not use uniform timing
    • Method: through the "end-start" signal through the response mode, the end signal of the previous operation is the start signal of the next operation signal
    • Advantages and disadvantages: Use as many beats as you need for state operations, and as many clocks as you need for micro-operations, there is no waste of idle clocks and idle beats, high work efficiency, fast command processing speed, but complex control is difficult to implement
  • 联合控制
    • The internal micro-operation and state operation of the CPU adopt synchronous control, and the external use asynchronous
    • The functional operations of most instructions are scheduled to be executed in the same machine cycle, and a small number of instructions that are too long or too short to be determined are asynchronous
    • Asynchrony on a synchronous basis

An example

• Assuming that the main frequency of the microprocessor CPU is 8MHZ, how many microseconds is its clock cycle? If each machine cycle contains 4 clock cycles, the average speed of CPU processing instructions is 0.8 MIPS. ask:

  • 1. What is the average instruction cycle in microseconds? How many machine cycles does it contain on average?
  • 2.If the microprocessor clock cycle is changed to 0.4μs, what is the average speed of processing instructions in MIPS?
  • 3. If the average speed of processing instructions needs to be 400,000 times/s, what is the main frequency of the microprocessor?

• 答案：

• Clock period=1/f=1/(8*10^6)=0.125μs

• 1. Average instruction cycle: 1/(0.8 10^6)=1.25μs Average machine cycle: 1.25/(4 0.125)=2.5

  • So an instruction cycle has 2.5 machine cycles, and a machine cycle has 4 clock cycles

• 2. Average speed: 1/(2.5 4 0.4)=0.25 strips/μs=0.25 MIPS

• 3. 0.4*10 ^{6=1/(2.5*4*T), T=0.25*10} -6(s), main frequency is 1/T=4MHZ

• 解析：

1. The reciprocal of the main frequency is the clock cycle
2.

3. The cycle is the number of seconds per second, and the frequency is how many times per second.
4. The average instruction speed: how many instructions are processed in one second, the average instruction cycle is the inverse of the average instruction speed. Note that MIPS is s, and finally converted to microseconds is *10 ^6
5. MIPS: 百万条/s----------ie条/μs

Microinstruction and its basic format

Microinstruction and its microcycle

• Micro instructions:
  • Concept: Refers to a collection of several micro-commands valid in a certain time unit
  • Usually the time to read the microinstruction is hidden in the execution of the previous microinstruction. In the T4 beat, both the microinstruction operation and the next microinstruction are read in parallel
  • 

Compatibility and mutual exclusion of micro commands

• Compatibility: Micro-commands that are allowed to be valid at the same time are called compatibility. Micro-commands are mutually exclusive.

A micro command (control signal) is a binary number, 1 is valid and 0 is invalid

The basic format of micro-commands

• Micro operation control domain + sequence control domain
• Micro-operation control domain:
  • Describe the corresponding control signals for microinstructions to perform micro operations
• Sequence control domain:
  • Describe the address of the next microinstruction after the microinstruction is processed
  • Because the sequence and jump are also divided into 2 fields
  • Test flag field and micro address field

If the test is established, the given micro address must be changed to realize the jump, otherwise the given micro address is the address of the next micro instruction

The relationship between machine instruction microprogram and microinstruction

• The instruction program address is related to the internal memory
• Microinstruction microprogram is address and control memory related
• A machine instruction corresponds to a micro program, this micro program is composed of several micro instruction sequences
• A machine instruction is divided into many micro-operations, and several micro-operations are controlled by one micro-instruction. All the micro-instructions together are called a micro-program, which corresponds to this entire machine instruction.

Coding method of micro commands

• Bit direct method: 1 means valid and 0 invalid, faster speed without decoding
• Uniform encoding method: encode all binary numbers together, and finally only display 1-2 valid through the decoder
• Segment coding method: combining direct coding and unified coding
  • Segmented directly
  • Sectional indirection: strengthen the restriction relationship between instructions
• Hybrid coding method: bit direct + segment direct
• Skill coding method (constant field control method):

Types of microinstruction format

• Horizontal micro-instructions: one bit corresponds to one, often direct, segmented and mixed bits are used to facilitate parallel operation
• Vertical micro-instructions: use unified coding method, mutually exclusive
  • Vertical type has multiple classifications like machine instructions

    • Transmission type

      • Micro-operation domain control format:微操作码+原编址+目的编址+读写等附加信息
      • 

    • Operational

      • Micro-operation domain control format:微操作码+左输入编址+右输入编址+移位等附加信息
      • 

    • Shift type

      • Micro-operation domain control format:微操作码+寄存器编址+移位次数+移位方式等附加信息

    • Transfer type

      • Micro-operation domain control format:微操作码+转移目标微地址+测试条件等附加信息

Comparison of horizontal type and vertical type

• The horizontal parallel operation ability is strong and the efficiency is high, the vertical type is opposite
  • The level can control multiple channels simultaneously for transmission
• Short horizontal execution time and long vertical time
  • Vertical decoding
• The horizontal microinstruction word is long, the micro program is short, and the vertical is the opposite
• Horizontal users are more difficult to master, vertical users are better

Basic requirements of microprogram design

• Small capacity of control memory
• Fast execution of microinstructions
• Microinstructions and microprograms are easy to modify and flexible