#The flower on the cliff, the more fragrant, the more impermanent.
Today I came to solve the solution to the problem encountered when using Robei EDA. I encountered this myself, and others asked me and I helped solve it. In the past few days, a senior came to me to write code to simulate the FPGA code. As a result, Modelsim on the computer had problems. So I used Robei's own simulation to give it to the senior. Seniors also find it very convenient, at least for beginners, it's easy to get started, unlike when I learned FPGA back then, it was bursting with tears.
include include files
In common Verilog code, you will encounter the writing method of including the include file, which is similar to defining some global constants, which is convenient to call. The wording in quartus is like this:
`include “sdram_para.v”In Robei EDA, include cannot be written directly in the Code section, but added in the definition column.
In the definition column on the right, you can see the "include" box, add the file name and suffix, and the file can be automatically included when the code is compiled. (Note that this file must be placed in the file path of the Robei module,