[FPGA] Roebi EDA common problem solving (2)-internal signal connection and function and two-dimensional array

#Zhizhiqiongli, study the ancients; Li Deliyan, no questions about the west and east.

I haven't written this series for a while. One is that I have encountered minor problems, most of which are my own problems, and the other is that I have been busy debugging the code, resulting in not much time to use EDA software. Today I mentioned this series again, which is also the problem and solution I encountered recently.

1. Connect internal signals in Robei EDA

Generally speaking, in the instantiation between code modules, there will be two cases of port instantiation. One is that the port is equipped with input and output lines, which is straightforward, and the other is that the port is equipped with the internal signal of the upper-level module. No more signal wires will be led out in higher-level modules after use. In Quartus or Vivado, these two operations are no different, but in Robei EDA, its usage is slightly different.

  1. Check the version. In some lower EDA versions, this operation is not available, and you need to download the latest version to cover it on the official website. How to check whether there is this operation, click on the pin of the robei top-level module to see if there is a Connect option in the disconnected properties, if there is, you can continue the operation; if not, you need to download the latest version to cover it on the official website.
  2. How to connect internal signals. Copy the internal signal name in the high-level module, click the port in the module image interface, and paste it into Connect in the property bar.

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Origin blog.csdn.net/Ninquelote/article/details/106679269