DC basic operation process
1. Create directories and files
[IC@IC lab1]$ ls -a
. .. common_setup.tcl dc_setup.tcl mapped rtl scripts .synopsys_dc.setup unmapped work
[IC@IC lab1]$ ls ./rtl
top.v
[IC@IC lab1]$ ls ./scripts
top.con
[IC@IC lab1]$ ls ./unmapped
[IC@IC lab1]$ ls ./mapped
[IC@IC lab1]$
Brief introduction of directory content:
/rtl 存放verilog设计文件 *.v
/script 存放约束文件 *.con
/unmapped 存放map之前的文件（目前是空目录）
/mapped 存放map之后的文件（目前是空目录）
.synopsys_dc.setup 在DC启动时自动source运行此文件的内容
common_setup.tcl 将User-defined 目录路径和文件路径存为变量
dc_setup.tcl 实现逻辑库和物理库的设置
(Find the library files contained in the DC installation directory:)
[IC@IC lab1]$ cd /opt/Synopsys/Synplify2015/
[IC@IC Synplify2015]$ pwd
/opt/Synopsys/Synplify2015
[IC@IC Synplify2015]$ find -name "*.db"
./auxx/syn/lc/corrlib_recipes/dummy.db
./doc/syn/ccsc/ccsc_examples/iq/ram/rams.db
./doc/syn/ccsc/ccsc_examples/iq/ram/ram.db
./doc/syn/ccsc/ccsc_examples/mem_control/ram/rams.db
./doc/syn/ccsc/ccsc_examples/mem_control/ram/ram.db
./doc/syn/examples/fsm/proc2.db
./doc/syn/examples/fsm/proc4.db
./doc/syn/examples/fsm/proc3.db
./doc/syn/examples/bc_view/verilog/db/example.db
./doc/syn/examples/bc_view/vhdl/db/example.db
./doc/syn/interfaces/cadence/tutorial/part2/top.pre.db
./doc/syn/interfaces/cadence/tutorial/LIB/class.db
./doc/syn/interfaces/valid/tutorial/part2/top.pre.db
./doc/syn/interfaces/viewlogic/tutorial/part2/top.pre.db
./doc/syn/interfaces/mentor/tutorial/part2/top.pre.db
./doc/syn/dv_tutorial/risc_design-flse-path/libs/core_typ.db
./doc/syn/dv_tutorial/risc_design/libs/core_typ.db
./doc/syn/dv_tutorial/risc_design-mult-clk/libs/core_typ.db
./doc/syn/tutorial/db/HOURS_FILTER.db
./doc/syn/tutorial/db/MUX.db
./doc/syn/tutorial/db/TOP.db
./doc/syn/tutorial/db/TIME_STATE_MACHINE.db
./doc/syn/tutorial/db/ALARM_BLOCK.db
./doc/syn/tutorial/db/ALARM_SM_2.db
./doc/syn/tutorial/db/ALARM_STATE_MACHINE.db
./doc/syn/tutorial/db/CONVERTOR_CKT.db
./doc/syn/tutorial/db/TIME_BLOCK.db
./doc/syn/tutorial/db/TIME_COUNTER.db
./doc/syn/tutorial/db/COMPARATOR.db
./doc/syn/tutorial/db/ALARM_COUNTER.db
./libraries/syn/nonlinear.db
./libraries/syn/lsi_lsc15.db
./libraries/syn/lsi_10k.db
./libraries/syn/lsi_7k.db
./libraries/syn/power_sample.db
./libraries/syn/tc6a_cbamc.db
./libraries/syn/class.db
./libraries/syn/power2_sample.db
./libraries/syn/lsi_9k.db
./libraries/syn/gtech.db
./libraries/syn/and_or.db
./libraries/syn/tc6a_cbacore.db
./libraries/syn/vhdlmacro.db
./libraries/syn/class_fpga.db
[IC@IC Synplify2015]$
2. Document content introduction
(1) common_setup.tcl file
############################################################################
# User-defined varibles for logical library setup in dc_setup.tcl
############################################################################
set ADDITIONAL_SEARCH_PATH "../ref/libs/mw_lib/sc/LM ./rtl ./scripts" ;
# Directories containing logic libraries, logical design and script files.
set TARGET_LIBRARY_FILES sc_max.db ; # Logical technology library file
set SYMBOL_LIBRARY_FILES sc.sdb ; # Symbol library file
############################################################################
# User-defined varibles for physical library setup in dc_setup.tcl
############################################################################
set MW_DESIGN_LIB TOP_LIB ; # User-defined Milkyway design library name
set MW_REFERENCE_LIB_DIRS ../ref/libs/mw_lib/sc ; # Milkyway reference libraries
set TECH_FILE ../ref/libs/tech/cb13_6m.tf ; # Milkyway technology
set TLUPLUS_MAX_FILE ../ref/libs/tlup/cb13_6m_max.tluplus ; # Max TLUPlus file
set MAP_FILE ../ref/libs/tlup/cb13_6m.map ; # Mapping file for TLUplus
echo "\ncommon_setup.tcl run to end...\n"
The common_setup.tcl file defines the name and name of the library, with the logical library above and the physical library below.
Line 5: Define the search path of the library. When the library is not found, look for
8 lines from this path : Define the library used by the target library (note that only a variable is defined)
Line 10: Define the graphics library variable
Line 15: Define the top level The variable name of the design library
17 line: define the milkyway (reference) library (location)
19 line: define the process library (location)
21 line: define the parasitic parameter library (location)
23 line: define the process library and parasitic parameter library Mapping library (location)
(2) dc_setup.tcl file
################################################################
# Logical Library Settings
################################################################
set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH"
set_app_var target_library $TARGET_LIBRARY_FILES
set_app_var link_library "* $target_library"
set_app_var symbol_library $SYMBOL_LIBRARY_FILES
################################################################
# Physical Library Settings
################################################################
set_app_var mw_reference_library $MW_REFERENCE_LIB_DIRS
set_app_var mw_design_library $MW_DESIGN_LIB
create_mw_lib -technology $TECH_FILE \
-mw_reference_library $mw_reference_library \
$mw_design_library
open_mw_lib $mw_design_library
set_tlu_plus_files -max_tluplus $TLUPLUS_MAX_FILE \
-tech2itf_map $MAP_FILE
echo "\ndc_setup.tcl run to end...\n"
The dc_setup.tcl file is to specify the library, rather than just defining it. set_app_var defines the internal variables of the DC. Compared with set, this command will check whether the setting name is spelled correctly.
Line 4~7: Specify the search path and the path and name of the various libraries.
Line 13: Specify the name of the milkyway (reference) library.
Line 14: Specify the name of the library currently designed.
Line 16: Create the milkyway library. The format is as shown above. Need process library, reference library, current design library
19 lines: open the current design library
20 lines: load parasitic parameters (library)
Explanation of various libraries :
The Link library and the target library are collectively referred to as the technology library (that is, the process library, which is customarily referred to as the comprehensive library). The technology library is provided by the semiconductor manufacturer and contains relevant cell information and design constraint standards. Among them:
Target library : During gate-level optimization and mapping, the cell that generates the netlist is provided, that is, the DC used to create the actual circuit library, provided by the fab.
Link library : Provides cells in the design netlist, which can use the same library as target_library, but DC does not use cells in the link library to synthesize the design. When DC reads the design, it automatically reads the library specified by the link library variable. When linking the design, DC first searches for libraries already in its memory, and then searches for the library specified by link library.
Note: When the read file is a gate-level netlist, you need to point link library to the library file that generated the gate-level netlist, otherwise DC will report an error because it does not know the function of the gate unit circuit in the netlist. The specific content in the process library will be specifically explained later.
Symbol library provides graphical symbols designed and implemented in Design Vision GUI. If you use script mode instead of GUI, this library does not need to specify Symbol library.
Synthetic library is Designware library. The translation of the name is a comprehensive library, but it is often called an IP library, not a literal translation. Special Designware library is required to be authorized (for example, the multi-stage pipeline multiplier), the default standard Designware is provided by the DC software vendor and does not need to be specified.
Create mw lib : When the physical synthesis of DC is mainly used, a physical library needs to be generated
(3).synopsys_dc.setup file
Run the above two scripts and print the current configuration
source common_setup.tcl
source dc_setup.tcl
# Verify Setting
echo "\n====================================="
echo "\nLibrary Settings:"
echo "search_path: $search_path"
echo "link_library: $link_library"
echo "target_library: $target_library"
echo "symbol_library: $symbol_library"
echo "mw_reference_library: $mw_reference_library"
echo "mw_design_library: $mw_design_library"
echo "\n====================================="
echo "\n.synopsys_dc.setup run to end...\n"
(4) ./rtl/top.v file
`timescale 1ns / 1ps
module Adder(
input clk,
input rst_n,
input [7:0] a,
input [7:0] b,
output reg [8:0] p
);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
p <= 0;
else
p <= a + b;
end
endmodule
(5) ./scripts/top.con file
(Operation may report errors, only a reference template is provided here)
set lib_name cb13fs120_tsmc_max
current_design Adder
# Reset all constraints
reset_design
# Create clock object and set uncertainty
create_clock -period 2 [get_ports clk]
set_clock_uncertainty 0.2 [get_clocks clk]
# Set constraints on input ports
suppress_message UID-401
set_driving_cell -library $lib_name -lib_cell sdcfq1 [remove_from_collection [all_inputs] [get_ports clk]]
set_input_delay 0.1 -max -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_input_delay 1.2 -max -clock clk [get_ports a_in]
# Set constraints on output ports
set_output_delay 1 -max -clock clk [all_outputs]
set_load [expr [load_of $lib_name/an02d0/A1] * 15] [all_outputs]
The reset_design in line 5 removes all previous constraints to prevent the following constraints from being affected.
3. Run DC
[IC@IC lab1]$ dc_shell -topo
Design Compiler Graphical
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)
Version K-2015.06 for linux64 - May 28, 2015
Copyright (c) 1988 - 2015 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited.
Initializing...
Starting shell in Topographical mode...
common_setup.tcl run to end...
Error: Technology file '../ref/libs/tech/cb13_6m.tf' does not exist. (MWUI-005)
Error: Cannot open library TOP_LIB for write. (MW-006)
Error: File '../ref/libs/tlup/cb13_6m_max.tluplus' does not exist or it is unreadable. (RCEX-070)
dc_setup.tcl run to end...
=====================================
Library Settings:
search_path: . /opt/Synopsys/Synplify2015/libraries/syn /opt/Synopsys/Synplify2015/minpower/syn /opt/Synopsys/Synplify2015/dw/syn_ver /opt/Synopsys/Synplify2015/dw/sim_ver /opt/Foundary_Library/TSMC90/aci/sc-x/synopsys ../ref/libs/mw_lib/sc/LM ./rtl ./scripts
link_library: * sc_max.db
target_library: sc_max.db
symbol_library: sc.sdb
mw_reference_library: ../ref/libs/mw_lib/sc
mw_design_library: TOP_LIB
=====================================
.synopsys_dc.setup run to end...
Initializing gui preferences from file /home/IC/.synopsys_dv_prefs.tcl
dc_shell-topo>
You can see that an Error appears when running dc_setup.tcl. This is because we do not have these library files for the time being and cannot load them correctly.
You can run the following two commands in dc_shell>:
check_library # 检查逻辑库和物理库的一致性，检查可能不会通过，结果不影响综合的话，可以忽略
checktluplus_files # 检查寄生参数文件和工艺库文件的一致性：（物理综合的时候需要检查），通过的话会有三个passed
4. Read in the design and view the design
read_file -format verilog ./rtl/top.v # 读入设计
current_design # 查看当前设计
current_design TOP # 设置当前设计为TOP，要综合哪个模块，就把哪个模块设置为当前设计
link # Link设计，查看当前要综合的设计是否缺少子模块，返回值是1，说明子模块完整
write -hierarchy -f ddc -out unmapped/top.ddc # 以ddc的格式保存未映射的设计，保存在unmapped文件夹中
list_designs # 查看内存中的设计，带*的设计为当前设计
list_libs # 查看内存中的库
5. Constraint design
source ./scripts/top.con
6. Comprehensive design
compile_ultra # 这是在拓扑模式下进行综合的命令
# 以下是综合后的检查（检查不通过的需要优化，这里只作为一般流程，没有进行优化）
report_qor > qor.report # 生成report信息并保存在qor.report文件中
report_constraint -all # 查看是否违规
report_timing # 查看时序报告
report_area # 查看面积情况
# 保存综合后的设计，保存在mapped文件夹
write -format verilog -hier -output ./mapped/top.gv
write -hierarchy -format ddc -output ./mapped/top.ddc
7. Summary
