DC comprehensive library, design object and DesignWare library
Standard cell library
Most digital design processes are semi-custom design processes based on standard units.
The standard cell library contains the physical information of the integrated model of logic cells such as inverters, buffers, NAND gates, NOR gates, NAND gates, latches, and flip-flops.
The standard unit is the logic that completes the general function and has the same height (the width can be different), which facilitates the automatic placement and routing of the digital back end.
Overview
An ASIC comprehensive library includes the following information:
(1) A series of cells (including the pins of the cells)
(2) The area of each cell (in deep sub-microns, generally expressed in square microns, in sub-micron processes, generally used For specific units, please consult the semiconductor manufacturer)
(3) The logic function of each output pin
(4) The transmission delay from each input to output, the transmission delay from output to output; from inout to output Transmission delay
Content and structure
Synopsys' process library is a .lib file, which is compiled by the Library Compiler software to generate a .db file. The process library file mainly includes the following information:
(1) Cell (information): (mainly) function, time (including the constraints of sequential devices, such as establishment and maintenance), area (the unit of area is not defined in it, but According to the law to understand, generally ask the semiconductor manufacturer), power consumption, testing, etc.
(2) Wire load models: resistance, capacitance, area.
(3) Operating conditions (Operating conditions): process (voltage and temperature scale factor k, which represents the scaling ratio of each parameter between different environments)
(4) Design rule constraints (Design): maximum and minimum Capacitance, maximum and minimum conversion time, maximum and minimum fan-out.
The structure of the process library is shown in the figure below:
For a more specific introduction to the process library, please refer to the reference materials at the end of the article.
DC design objects
For a Verilog code module, we know what the name of the module is, what is the function of this module, what ports the module has, and so on. But for DC, it doesn't understand it like we do. Give it a Verilog module and treat the content of this module as a design object (object for short).
The corresponding relationship between the Verilog module and the objects supported by DC is shown in the figure below:
DC supports 8 design objects :
When DC reads the design, you can view these objects with the following commands:
get_ports,_pins,_designs,_cells,_nets,_clocks
all_inputs,_outputs,_clocks,_registers
set pci_ports [get_ports “Y??M Z*”]
echo $pci_ports
query_objects $pci_ports
sizeof_collection $pci_ports
set pci_ports [add_to_collection $pci_ports [get_ports CTRL*]]
set all_input_except_clk [remove_from _collection [all_inputs] [get_ports CLK]]
filter_collection [get_cells *] “ref_name=~AN*”
get_cells * -filter “don’t_touch == true”
list_attributes -application -class <object_type>
Query: access a certain object,
Sizeof: check the size of a certain (object) collection.
Objects have certain attributes , such as:
port attributes include: direction, drive unit, load, maximum capacitance constraints, etc.
cell attributes include: hierarchical, non-touch, etc.
Clock attributes include: period, jitter Wait
Writing constraints is to restrict the attributes of the design object.
DesignWare library
DesignWare is an Intellectual Property (IP) library provided by Synopsys. IP library is divided into synthesizable IP library (Synthesizable IP, SIP), verification IP library (Verification IP, VIP) and manufacturer library (Foundry Libraries).
The IP library contains a variety of different types of devices, which can be used to design and verify ASIC, SoC and FPGA. There are the following devices in the library:
·Building Block IP (data path, data integrity, DSP, test circuit, etc.).
·AMBA bus structure (Bus Fabric), peripheral devices (Peripherals) and corresponding verification IP.
·Memory portfolio (memory controller, memory BIST, memory model, etc.).
· Validation model of universal bus and standard I/O interface (PCI Express, PCI-X, PCI and USB).
·Microprocessor and DSP core provided by the most important star IP supplier in the industry.
· Foundry Libraries.
·Board-level verification IP
·Microcontrollers (such as 8051 and 6811).
·and many more
Mainly introduce the designware foundation library integrated in the DC synthesis tool. All IPs are pre-verified, reusable, parameterized, synthesizable, and are not subject to process constraints.
Some commonly used designware foundation library units are shown in the following table (for more information, please refer to reference materials):
To use the devices in the IP library, you can use operator inferencing or functional inferencing. The inference method of operation signs is to directly use operation signs such as "+, -, *, >, == and <" in the design. The function inference method is to instantiate a certain arithmetic unit in DesignWare in the design, for example, directly specify the DWF_mult_tc, DWF_div_uns and other units in the library.
Since all the devices in the DesignWare library have been verified in advance, we can use this IP library to design faster, design higher quality, increase design productivity and design reusability, and reduce design risks and technical difficulties risk. For each operation symbol, generally speaking, there will be multiple structures (algorithms) in the DesignWare library to complete the operation. This allows the DC to evaluate the speed/area trade-off during the optimization process and select the best implementation result. For a given function, if multiple DesignWare circuits can implement it, Design Compiler will select the circuit that best meets the design constraints. In addition, the use of the DW Foundation library in DesignWare requires a license . The DW Foundation library provides better design quality (Quality of Result).
The method of using IP in DesignWare is shown below:
Design Compile automatically selects and optimizes arithmetic devices. For arithmetic operations, we do not need to specify the standard (basic) comprehensive library standard.sldb in DC. The standard integrated library standard.sldb contains built-in HDL arithmetic symbols, and DC will automatically use this library during synthesis. If we want to use additional IP libraries with higher performance, such as DW_foundation.sldb, we must specify these libraries as follows:
#Specify for use during optimization
set synthetic_library dw_foundation.sldb
#Specify for cell resolution during link
lappend link_library $synthetic_library
Reference
https://www.cnblogs.com/IClearner/p/6622524.html