20210123 Zhang Dajia MCU VHDL Common Syntax---- Port map and OPEN

VHDL common syntax ---- Port map and OPEN

FPGA---Basic Skills Daily Record Memo

Two ways to map the PORTS of a COMPONENT during its instantiation:

1 The 　first variable and pin association method Positional mapping , ports x and y correspond to a and b, respectively.

COMPONENT inverter IS
    PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC); 
END COMPONENT; 
... 

U1 : inverter PORT MAP (X,Y);

2　The second variable associated pin and ways 　Nominal Mapping Would BE at The following:

U1: inverter PORT MAP (x => a, y => b);

  Positional mapping is easier to write, but nominal mapping is less error-prone.

 3 The　third way to associate variables and pins can have --- open keyword Ports can also be left unconnected (using the keyword OPEN ). 

U2: my_circuit PORT MAP (X => a, y => b, z => OPEN);

4 　　How Bit by location =>   Used to ASSIGN values to the Vector or with keyword Individual Others

signal Data_Bus : std_logic_vector (15 downto 0);
... ...

-- 1st way
Data_Bus <= (15 | 7 downto 0 => '1', others => '0');

-- 2nd way
Data_Bus (15 | 7 downto 0) <= '1';
Data_Bus (14 downto 8) <= '0';

 

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