Computer composed of LF
1. Assuming that the capacity of the microprogram controller is 1024×48 bits, the microprogram can be transferred in the entire control memory. There are 4 branch points in the finite state machine that reflects the state transition of all instructions. The horizontal microinstruction format is adopted. The determination method is used to determine the next micro-address, that is, the micro-address is determined by a special lower address field.
1) Design the microinstruction format to explain the meaning and number of bits of each field;
2) Encode the transfer control field.
(1) Solution: The capacity of the microprogram controller is 1024 × 48, which means that the address field has 10 bits;
there are 4 branch points, which means that 5 clocks need to be controlled, and the transfer field has 3 bits; the
micro-op code field has 48 -10-3 = 35 bits
(2) Transfer control field coding: (Note: the coding method is not unique, as long as it is correct)
000: The address indicated by the next address field is used as the next micro address
100: The next micro address
101 is selected according to the conditions at branch 1 : Select the next micro address
according to the conditions at branch 2 110: Select the next micro address according to the conditions at branch 3
111: Select the next micro address according to the conditions at branch 4
2. The CPU frequency of a certain computer is 500MHz, and the CPI is 5. Assuming that the data transmission rate of a certain peripheral is 0.5MB/s, the data transmission with the host is carried out by interrupt mode, the transmission unit is 32 bits, and the corresponding interrupt service program contains 18 One instruction, interrupt response and other overheads are equivalent to the execution time of two instructions. Answer the following questions and ask for the calculation process.
1) In interrupt mode, what percentage of the total CPU time is the CPU time spent on the peripheral I/O?
2) When the data transfer rate of the peripheral reaches 5MB/s, use DMA to transfer data instead. Assuming that the block size of each DMA transfer is 5000B, and the total overhead of DMA pre-processing and post-processing is 500 clock cycles, what percentage of the total CPU time is used by the CPU for peripheral I/O? (Assuming that there is no memory access conflict between DMA and CPU)
Solution:
(1) The number of clock cycles for each interrupt processing is (18+2) × 5 = 100
The data transmitted by the peripheral is 0.5MB/s, and each interruption transmits 4 bytes, the
number of interruptions = 0.5MB / 4B = 125000 times
100 × 125000 = 12.5M clock cycles
CPU frequency is 500MHZ, the time is 12.5/500=2.5%
(2) 5MB/1000B = 1000 times
500 × 1000 = 0.5M
0.5M / 500M = 0.1%
3. The registers and internal organization structure of the "very simple CPU" are as follows: the storage space is 64B, the programmer can access the register AC, and the 6-bit address register AR, 6-bit program counter PC, and 8-bit data register DR for work. , 2-bit instruction register IR.
The instruction set structure is as follows:
(1) Assuming that the initial PC=0, AC=25H, the contents of each memory unit are as follows. After the program runs for 5 instruction cycles, AC=? write out the process of each step.
| unit number | content |
|---|---|
| 0 | 01000111 |
| 1 | 00000110 |
| 2 | 11101010 |
| 3 | 10000001 |
| 4 | 10101010 |
| 5 | 01010101 |
| 6 | 00000011 |
| 7 | 10101010 |
| 8 | 11111100 |
pc = 0，内容 = 01 000 111 执行AND
内容地址 = 000 111
M[000 111] = M[ 7 ] = 1010 1010
AC = 25H = 0010 0101
AC ^ 1010 1010 = 0010 0000 = 20H
pc=1,内容 = 00000110 执行 ADD
内容地址 = 000110 = 6
AC + 00000011 = 0010 0000 + 00000011
= 0010 0011 = 23H
pc=2，内容 = 11101010 执行INC
AC + 1 = 0010 0100 = 24H
pc =3 ，内容 = 10000001 执行 JMP
内容地址 = 000001 = 1 跳到1号单元
pc = 4，AC + 00000011 = 27H
故执行5个周期后，AC = 27H
(2) Draw the CPU state diagram.
Because the instruction register IR has two bits, the IR instructions needed to complete the four operations are 00, 01, 10, and 11 respectively.
(3) Write the operation statements of each state in RTL language.
FETCH1: AR←PC (addressing)
FETCH2: DR←M, PC←PC+1
FETCH3: IR←DR[7…6], AR←DR[5…0]
ADD1: DR←M
ADD2: AC←AC＋DR
AND1: DR←M
AND2: AC←AC∧DR
JMP1: PC ← DR [5… 0]
INC1: AC←AC＋1